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CY8CPLC20 powerline communication solution cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-48325 rev. *j revised june 29, 2011 features powerline communication solution ? integrated powerline modem phy ? frequency shift keying modulation ? configurable baud rates up to 2400 bps ? powerline optimized network protocol ? integrates data link, transport, and network layers ? supports bidirectional half duplex communication ? 8-bit crc error detection to minimize data loss ? i 2 c enabled powerline application layer ? supports i 2 c frequencies of 50, 100, and 400 khz ? reference designs for 110 v/240 v ac and 12 v/24 v ac/dc powerlines ? reference designs comply with cenelec en 50065-1:2001 and fcc part 15 powerful harvard-architecture processor ? m8c processor speeds to 24 mhz ? two 8x8 multiply, 32-bit accumulate programmable system resources (psoc ? blocks) ? 12 rail-to-rail analog psoc blocks provide: ? up to 14-bit adcs ? up to 9-bit dacs ? programmable gain amplifiers ? programmable filters and comparators ? 16 digital psoc blocks provide: ? 8 to 32-bit timers, counters, and pwms ? crc and prs modules ? up to four full duplex uarts ? multiple spi? masters or slaves ? connectable to all gpio pins ? complex peripherals by combining blocks flexible on-chip memory ? 32 kb flash program storage 50,000 erase or write cycles ? 2 kb sram data storage ? eeprom emulation in flash programmable pin configurations ? 25 ma sink, 10 ma source on all gpios ? pull-up, pull-down, high z, strong, or open drain drive modes on all gpio ? up to 12 analog inputs on all gpios ? configurable interrupt on all gpios additional system resources ? i 2 c slave, master, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low-voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference complete development tools ? free development software (psoc designer?) ? full-featured in-circuit emulator (ice) and programmer ? full-speed emulation ? complex breakpoint structure ? 128 kb trace memory ? complex events ? c compilers, assembler, and linker CY8CPLC20 powerline network protocol physical layer fsk modem ac/dc powerline coupling circuit (110v/240v ac, 12v/24v ac/dc etc.) powerline powerline communication solution powerline transceiver packet programmable system resources digital and analog peripherals psoc core additional system resources mac, decimator, i2c, spi, uart etc. plc core embedded application logic block diagram
CY8CPLC20 document number: 001-48325 rev. *j page 2 of 56 1. contents plc functional overview ................................................ 3 robust communication using cypress?s plc solution 3 powerline modem phy ............................................... 3 network protocol ......................................................... 4 psoc core ......................................................................... 8 programmable system resources .............................. 8 additional system resources ................................... 11 getting started ................................................................ 11 application notes ...................................................... 11 development kits ...................................................... 11 training ..................................................................... 11 cypros consultants .................................................. 11 solutions library ........................................................ 11 technical support ..................................................... 11 development tools ........................................................ 12 psoc designer software subsyst ems .......... ............ 12 in-circuit emulator (ice) ........................................... 12 designing with psoc designer ..................................... 13 select components ................................................... 13 configure components .......... .............. .............. ....... 13 organize and connect .............. .............. ........... ....... 13 generate, verify, and debug ..................................... 13 plc user modules ................. ................................... 14 pin information ............................................................... 15 28-pin part pinout ..................................................... 15 48-pin part pinout ..................................................... 16 100-pin part pinout (on-chip debug) ....................... 17 register reference ......................................................... 19 register conventions ................................................ 19 register mapping tables .......................................... 19 electrical specifications ................................................ 22 absolute maximum ratings ... .................................... 22 operating temperature ............................................. 22 dc electrical characteristics ..................................... 23 ac electrical characteristics ..................................... 32 packaging information ................................................... 41 packaging dimensions .............................................. 41 thermal impedances ................................................. 44 capacitance on crystal pins .. ............. .............. ........ 44 solder reflow peak temperat ure ............................. 44 development tool selection .. .............. .............. ........... 45 software .................................................................... 45 development kits ...................................................... 45 evaluation kits ........................................................... 46 device programmers ............. .................................... 46 ordering information ...................................................... 47 ordering code definitions ..... .................................... 47 acronyms ........................................................................ 48 acronyms used ......................................................... 48 reference documents .................................................... 49 document conventions ................................................. 49 units of measure ....................................................... 49 numeric conventions ............ .................................... 49 glossary .......................................................................... 50 document history page ................................................. 55 sales, solutions, and legal information ...................... 56 products .................................................................... 56 psoc solutions ......................................................... 56
CY8CPLC20 document number: 001-48325 rev. *j page 3 of 56 2. plc functional overview the CY8CPLC20 is an integr ated powerline communication (plc) chip with the powerline modem phy and network protocol stack running on the same device. apart from the plc core, the CY8CPLC20 also offers cypress's revolutionary psoc technology that enabl es system designers to integrate multiple functions on the same chip. 2.1 robust communication using cypress?s plc solution powerlines are available everywhere in the world and are a widely available communication medium for plc technology. the pervasiveness of powerlines also makes it difficult to predict the characteristics and operation of plc products. because of the variable quality of powerlines around the world, implementing robust communication has been an engineering challenge for years. the cypress plc solution enables secure and reliable communications. cypress plc features that enable robust communication over powerlines include: integrated powerline phy modem with optimized filters and amplifiers to work with lossy high voltage and low voltage powerlines. powerline optimized network pr otocol that supports bidirec- tional communication with acknow ledgement-based signaling. in case of data packet loss due to bursty noise on the powerline, the transmitter has the capability to retransmit data. the powerline network protocol also supports an 8-bit crc for error detection and data packet retransmission. a carrier sense multiple access (csma) scheme is built into the network protocol that minimizes collisions between packet transmissions on the powerline and supports multiple masters and reliable communication on a bigger network. 2.2 powerline modem phy figure 2-1. physical layer fsk modem the physical layer of the cypress plc solution is implemented using an fsk modem that enables half duplex communication on any high voltage and low voltage powerline. this modem supports raw data rates up to 2400 bps. a block diagram is shown in figure 2-2 figure 2-2. physical layer fsk modem block diagram 2.2.1 transmitter section digital data from the network layer is serialized by the digital transmitter and fed as input to the modulator. the modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic ?1? or low level logic ?0?. it then generates a square wave at 133.3 khz (logic ?0?) or 131.8 khz (logic ?1?), wh ich is fed to the programmable gain amplifier to generate fsk m odulated signals. this enables tunable amplification of the signal depending on the noise in the channel. the logic ?1? frequency can also be configured as 130.4 khz for wider fsk deviation. 2.2.2 receiver section the incoming fsk signal from the powerline is input to a high frequency (hf) band pass filter t hat filters out-of-band frequency components and outputs a filter ed signal within the desired spectrum of 125 khz to 140 khz for further demodulation. the mixer block multiplies the filtered fsk signals with a locally generated signal to produce heterodyned frequencies. CY8CPLC20 powerline network protocol physical layer fsk modem powerline communication solution powerline transceiver packet programmable system resources digital and analog peripherals psoc core additional system resources mac, decimator, i2c, spi, uart etc. plc core embedded application network protocol coupling circuit hf band pass filter hysteresis comparator digital receiver if band pass filter low pass filter mixer correlator powerline modem phy modulator local oscillator logic ?1? or logic ?0? square wave at fsk frequencies digital transmitter transmitter receiver local oscillator rx amplifier programmable gain amplifier external low pass filter
CY8CPLC20 document number: 001-48325 rev. *j page 4 of 56 the intermediate frequency (if) band pass filters further remove out-of-band noise as required for further demodulation. this signal is fed to the correlator, which produces a dc component (consisting of logic ?1? and ?0?) and a higher frequency component. the output of the correlator is fe d to a low pass filter (lpf) that outputs only the demodulated digital data at 2400 baud and suppresses all other higher frequency components generated in the correlation process. the output of the lpf is digitized by the hysteresis comparator. this eliminates the effects of correlator delay and false logic triggers due to noise. the digital receiver deserializes this data and outputs to the network layer for interpretation. 2.2.3 coupling circuit reference design the coupling circuit couples low voltage signals from the CY8CPLC20 to the powerline. the topology of this circuit is determined by the voltage on the powerline and design constraints mandated by powerline usage regulations. cypress provides reference designs for a range of powerline voltages including 110 v/240 v ac and 12 v/24 v ac/dc. the CY8CPLC20 is capable of data communication over other ac/dc powerlines as well with t he appropriate external coupling circuit. the 110 v ac and 240 v ac designs are compliant to the following powerline usage regulations: fcc part 15 for north america en 50065-1:2001 for europe 2.3 network protocol cypress?s powerline optimized network protocol performs the functions of the data link and network layers in an iso/osi-equivalent model. figure 2-3. powerline network protocol the network protocol implemented on the CY8CPLC20 supports the following features: bidirectional half-duplex communication master-slave or peer-to-peer network topologies multiple masters on powerline network 8-bit logical addressing supports up to 256 powerline nodes 16-bit extended logical addressing supports up to 65536 powerline nodes 64-bit physical addressing supports up to 2 64 powerline nodes individual, broadcast or group mode addressing carrier sense multiple access (csma) full control over transmission parameters ? acknowledged ? unacknowledged ? repeated transmit 2.3.1 csma and timing parameters csma ? the protocol provides t he random selection of a period between 85 and 115 ms (out of seven possible values in this range) in which the band-in-use (biu) detector must indicate that the line is not in use, before attempting a transmission. biu ? a band-in-use detector, as defined under cenelec en 50065-1, is active whenever a si gnal that exceeds 86 dbmvrms anywhere in the range 131.5 khz to 133.5 khz is present for at least 4 ms. this threshold can be configured for different end-system applications not requiring cenelec compliance.the modem tries to retransmit after every 85 to 115 ms when the band is in use. the transmitter times out after 1.1 seconds to 3 seconds (depending on the noise on the powerline) and generates an interrupt to indicate that the transmitter was unable to acquire the powerline. 2.3.2 powerline transceiver packet the powerline network protocol defines a powerline transceiver (plt) packet structure, which is used for data transfer between nodes across the powerline. packet formation and data transmission across the powerline network are implemented internally in CY8CPLC20. a plt packet is divided into a variable length header (minimum 6 bytes to maximum 20 bytes, depending on address type), a variable length payload (mini mum 0 bytes to maximum 31 bytes), and a packet crc byte. this packet (preceded by a one byte preamble ?0xab?) is then transmitted by the powerline modem phy and the external coupling circuit across the powerline. the format of the plt packet is shown in table 2-1 on page 5 . CY8CPLC20 powerline network protocol physical layer fsk modem powerline communication solution powerline transceiver packet programmable system resources digital and analog peripherals psoc core additional system resources mac, decimator, i2c, spi, uart etc. plc core embedded application
CY8CPLC20 document number: 001-48325 rev. *j page 5 of 56 table 2-1. powerline transceiver (plt) packet structure 2.3.3 packet header the packet header contains the first 6 bytes of the packet when 1-byte logical addressing is used. when 8-byte physical addressing is used, the source and destination addresses each contain 8 bytes. in this case, the header can consist of a maximum of 20 bytes. unused fields marked rsvd are for future expansion and are transmitted as bit 0. ta b l e 2 - 2 describes the plt packet header fields in detail. table 2-2. powerline transceiver (plt) packet header 2.3.4 payload the packet payload has a length of 0 to 31 bytes. payload content is user defined and can be read or written through i 2 c. 2.3.5 packet crc the last byte of the packet is an 8-bit crc value used to check packet data integrity. this c rc calculation includes the header and payload portions of the packet and is in addition to the powerline packet header crc. 2.3.6 sequence numbering the sequence number is increased for every new unique packet transmitted. if in acknowledg ed mode and an acknowledgment is not received for a given packe t, that packet is re-transmitted (if tx_retry > 0) with the sa me sequence number. if in unacknowledged mode, the packet is transmitted (tx_retry + 1) times with the same sequence number. if the receiver receives consec utive packets from the same source address with the same sequence number and packet crc, it does not notify the host of the reception of the duplicate packet. if in acknowledged mode, it still sends an acknowledgment so that the transmitter knows that the packet was received. 2.3.7 addressing the CY8CPLC20 has three modes of addressing: logical addressing: every CY8CPLC20 node can have either a 8-bit logical address or a 16-bit logical address. the logical address of the plc node is set by the local application or by a remote node on the powerline. physical addressing: every CY8CPLC20 has a unique 64-bit physical address. group addressing: this is explained in the next section. 2.3.8 group membership group membership enables the user to multicast messages to select groups. the CY8CPLC20 supports two types of group addressing: single group membership ? the network protocol supports up to 256 different groups on the network in this mode. in this mode, each plc node can only be part of a single group. for example, multiple plc nodes can be part of group 131. multiple group membership ? the network protocol supports eight different groups in this mode and each plc node can be a part of multiple groups. for example, a single plc node can be a part of group 3, group 4, and group 7 at the same time. both these membership modes can also be used together for group membership. for example, a single plc node can be a part of group 131 and also multiple groups such as group 3, group 4, and group 7. the group membership id for broadcasting messages to all nodes in the network is 0x00. the service type is always set to unacknowledgment mode in group addressing mode. this is to avoid acknowledgment flooding on the powerline during multicast. 2.3.9 remote commands in addition to sending normal data over the powerline, the cy8cplc10 can also send (and request) control information to (and from) another node on the network. the type of remote command to transmit is set by the tx_commandid register and when received, is stored in the rx_commandid register. when a control command (command id = 0x01-0x08 and 0x0c-0x0f) is received, the protocol automatically processes the packet (if lock_configuration is '0'), responds to the initiator, and notifies the host of the successful transmission and reception. byte offset bit offset 765 4 3 2 1 0 0x00 sa type da type service type rsvd rsvd response rsvd 0x01 destination address (8-bit logical, 16-bit extended logical or 64-bit physical) 0x02 source address (8-bit logical, 16-bit extended logical or 64-bit physical) 0x03 command 0x04 rsvd payload length 0x05 seq num powerline packet header crc 0x06 payload (0 to 31 bytes) powerline transceiver packet crc field name no. of bits tag description sa type 1 source address type 0 ? logical addressing 1 ? physical addressing da type 2 destination address type 00 ? logical addressing 01 ? group addressing 10 ? physical addressing 11 ? invalid service type 1 0 ? unacknowledged messaging 1 ? acknowledged messaging response 1 response 0 - not an acknowledgement or response packet 1 - acknowledgement or response packet seq num 4 sequence number 4-bit unique identifier for each packet between source and desti- nation. header crc 4 4-bit crc value. this enables the receiver to suspend receiving the rest of the packet if its header is corrupted
CY8CPLC20 document number: 001-48325 rev. *j page 6 of 56 when the send data command (id 0x09) or request for data command (id 0x0a) is received, the protocol replies with an acknowledgment packet (if tx_service_type = '1'), and notify the host of the new received data. if the initiator doesn't receive the acknowledgment packet within 500ms, it notifies the host of the no acknowledgment received condition. when a response command (id 0x0b) is received by the initiator within 1.5s of sending the request for data command, the protocol notifies the host of the successful transmission and reception. if the response command is not received by the initiator within 1.5s, it notifies the host of the no response received condition. the host is notified by updating the appropriate values in the int_status register (including status_value_change). the command ids 0x30-0xff can be used for custom commands that would be processed by the external host (e.g. set an led color, get a temperature/voltage reading). the available remote commands are described in ta b l e 2 - 3 with the respective command ids. table 2-3. remote commands cmd id command name description payload (tx data) response (rx data) 0x01 setremote_txenable sets the tx enable bit in the plc mode register. rest of the plc mode register is unaffected 0 - disable remote tx 1 - enable remote tx if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x03 setremote_extendedaddr set the addressing to extended addressing mode 0 - disable extended addressing 1 - enable extended addressing if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x04 setremote_logicaladdr assigns the specified logical address to the remote plc node if ext address = 0, payload = 8-bit logical address if ext address = 1, payload = 16-bit logical address if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x05 getremote_logicaladdr get the logical address of the remote plc node none if remote tx enable = 0, response = none if remote tx enable = 1, {if ext address = 0, response = 8-bit logical address if ext address = 1, response = 16-bit logical address} 0x06 getremote_physicaladdr get the physical address of the remote plc node none if remote tx enable = 0, response = none if remote tx enable = 1, response = 64-bit physical address 0x07 getremote_state requ est plc_mode register content from a remote plc node none if remote tx enable = 0, response = none if remote tx enable = 1, response = remote plc mode register 0x08 getremote_version get t he version number of the remote node none if tx enable = 0, response = none if tx enable = 1, response = remote version register 0x09 sendremote_data transmit data to a remote node. payload = local tx data if local service type = 0, response = none if local service type = 1, response = ack
CY8CPLC20 document number: 001-48325 rev. *j page 7 of 56 0x0a requestremote_data request data from a remote node payload = local tx data if local service type = 1, response = ack then, the remote node host must send a responseremote_data command. the response must be completely transmitted within 1.5s of receiving the request. otherwise, the requesting node will time out. 0x0b responseremote_data transmit response data to a remote node. payload = local tx data none 0x0c setremote_biu enables /disables biu function- ality at the remote node 0 - enable remote biu 1 - disable remote biu if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x0d setremote_thresholdvalue sets the threshold value at the remote node 3-bit remote threshold value if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x0e setremote_groupmembership sets the group membership of the remote node byte0 - remote single group membership address byte1- remote multiple group membership address if remote lock config = 0, response = 00 (success) if remote lock config = 1, response = 01 (denied) 0x0f getremote_groupmembership ge ts the group membership of the remote node none if remote tx enable = 0, response = none if remote tx enable = 1, response = byte0 - remote single group membership address byte1- remote multiple group membership address 0x10 - 0x2f reserved 0x30 - 0xff user defined command set table 2-3. remote commands (continued) cmd id command name description payload (tx data) response (rx data)
CY8CPLC20 document number: 001-48325 rev. *j page 8 of 56 3. psoc core the CY8CPLC20 is based on the cypress psoc ? 1 architecture. the psoc platform consists of many programmable system-on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low-cost single-chip programmable device. psoc devices include configurable blocks of analog and digita l logic, and programmable interconnects. this architecture enables the user to create customized peripheral conf igurations that match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and configurable i/os are included in a range of convenient pinouts and packages. the psoc architecture, as shown in figure 3-1 , consists of four main areas: psoc core, digi tal system, analog system, and system resources. configurable global busing enables all the device resources to be combin ed into a complete custom system. the CY8CPLC20 family can have up to five i/o ports that connect to the global digital and analog interconnects, providing access to 16 digita l blocks and 12 analog blocks. the psoc core is a powerful engine that supports a rich feature set. the core includes a cpu, me mory, clocks, and configurable gpio (general purpose i/o). figure 3-1. psoc core the m8c cpu core is a powerful processor with speeds up to 24 mhz, providing a 4 mips 8-bit harvard architecture microprocessor. the cpu uses an interrupt controller with 25 vectors, to simplify programming of realtime embedded events. program execution is timed and protected using the included sleep and watchdog timers (wdt). memory encompasses 32 kb of flash for program storage, 2 kb of sram for data storage, and up to 2 kb of eeprom emulated using flash. program flash uses f our protection levels on blocks of 64 bytes, enabling customized software ip protection. the psoc device incorporates flexible internal clock generators, including a 24 mhz internal main oscillator (imo) accurate to 2.5 percent over temperature and vo ltage. the 24 mhz imo can also be doubled to 48 mhz for the digital system use. a low power 32 khz internal low speed oscillator (ilo) is provided for the sleep timer and wdt. if crystal accuracy is desired, the eco (32.768 khz external crystal oscillator) is available for use as a real time clock (rtc) and can optionally generate a crystal-accurate 24 mhz system clock using a pll. when operating the powerline transceiv er (plt) user module, the eco must be selected to ensure accura te protocol timi ng. the clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the psoc device. psoc gpios provide connection to the cpu, digital, and analog resources of the device. each pi n?s drive mode may be selected from eight options, enabling great flexibility in external interfacing. every pin also has the capability to generate a system interrupt on high level, lo w level, and c hange from last read. 3.1 programmable system resources figure 3-2. programmable system resources digital system sram 2k interrupt controller sleep and watchdog multiple clock sources (includes imo, ilo, pll, and eco) global digital interconnect global analog interconnect psoc core cpu core (m8c) srom flash 32k digital block array two multiply accums. internal voltage ref. digital clocks por and lvd system resets decimator system resources analog system analog block array analog ref. analog input muxing i c 2 port 7 port 6 port 5 port 4 port 3 port 2 port 1 port 0 analog drivers system bus powerline network protocol physical layer fsk modem powerline transceiver packet programmable system resources digital and analog peripherals psoc core additional system resources mac, decimator, i2c, spi, uart etc. plc core embedded application
CY8CPLC20 document number: 001-48325 rev. *j page 9 of 56 3.1.1 the digital system the digital system contains 16 digital psoc blo cks. each block is an 8-bit resource that can be used alone, or combined with other blocks to form 8- , 16-, 24-, and 32-bi t peripherals called user modules. digital peripheral configurations include: pwms (8- to 32-bit) pwms with dead band (8- to 32-bit) counters (8- to 32-bit) timers (8- to 32-bit) uart 8 bit with selectable parity (up to four) spi master and slave (up to four each) i 2 c slave and multi-master (one available as a system resource) cyclical redundancy checker and generator (8- to 32-bit) irda (up to four) pseudo random sequence generators (8- to 32-bit) the digital blocks can be connected to any gpio through a series of global buses that can route any signal to any pin. the buses also enable signal multiplexing and perform logic operations. this configurability frees your designs from the constraints of a fixed peripheral controller. figure 3-3. digital system block diagram digital system to system bus d i g i t a l c l o c k s f r o m c o r e digital psoc block array to analog system 8 row input configuration row output configuration 8 8 8 row 1 dbb10 dbb11 dcb12 dcb13 row input configuration 4 4 row output configuration row input configuration row output configuration row 2 dbb20 dbb21 dcb22 dcb23 4 4 row 0 dbb00 dbb01 dcb02 dcb03 4 4 row input configuration row output configuration row 3 dbb30 dbb31 dcb32 dcb33 4 4 gie[7:0] gio[7:0] goe[7:0] goo[7:0] global digital interconnect po r t 7 po r t 6 po r t 5 po r t 4 po r t 3 po r t 2 po r t 1 po r t 0
CY8CPLC20 document number: 001-48325 rev. *j page 10 of 56 3.1.2 the analog system the analog system co ntains 12 configurable blocks, each containing an opamp circuit, enabling the creation of complex analog signal flows. analog peripherals are very flexible and can be customized to support specific application requirements. some of the more common psoc analog functions (most available as user modules) are: analog-to-digital converters (up to four, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and sar) filters (2, 4, 6, or 8 pole band pass, low pass, and notch) amplifiers (up to four, with selectable gain to 48x) instrumentation amplifiers (up to two, with selectable gain to 93x) comparators (up to four, with 16 selectable thresholds) dacs (up to four, with 6- to 9-bit resolution) multiplying dacs (up to four, with 6- to 9-bit resolution) high current output drivers (4 with 40 ma drive as a core resource) 1.3 v reference (as a system resource) dtmf dialer modulators correlators peak detectors many other topologies possible analog blocks are provided in colu mns of three, which includes one continuous time (ct) and two switched capacitor (sc) blocks, as shown in the figure 3-4 . figure 3-4. analog system block diagram acb00 acb01 block array array input configuration aci1[1:0] aci2[1:0] acb02 acb03 asc12 asd13 asd22 asc23 asd20 aci0[1:0] aci3[1:0] p0 [ 6 ] p0 [ 4 ] p0 [ 2 ] p0 [ 0 ] p2 [ 2 ] p2 [ 0 ] p2 [ 6 ] p2 [ 4 ] refin agndin p0 [ 7 ] p0 [ 5 ] p0 [ 3 ] p0 [ 1 ] p2 [ 3 ] p2 [ 1 ] re f e r e n ce generators a gndin ref in bandgap ref hi ref lo agnd asd11 asc21 asc10 interface to digital system m8c interface (address bus, data bus, etc.) analog reference
CY8CPLC20 document number: 001-48325 rev. *j page 11 of 56 3.2 additional system resources figure 3-5. CY8CPLC20: additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. resources include a multiplier, decimator, low-voltage detection, and power on reset. the following statements describe the merits of each system resource. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks are generated using digital psoc blocks as clock dividers. multiply accumulate (mac) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. the decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma adcs. the i 2 c module provides 100 and 400 khz communication over two wires. slave, master, and multi-master modes are supported. low-voltage detection (lvd) interrupts signal the application of falling voltage levels, while the advanced power on reset (por) circuit eliminates t he need for a system supervisor. an internal 1.3v reference provides an absolute reference for the analog system, includ ing adcs and dacs. 4. getting started the quickest way to understand cypress?s powerline communi- cation offering is to read this data sheet and then use the psoc designer integrated development environment (ide). the latest version of psoc designer can be downloaded from http://www.cypress.com . this data sheet is an overview of the CY8CPLC20 integrated circuit and presents specific pin, register, and electrical specifications. for in depth information, along with detailed programming details, see the plc technical reference manual. for up-to-date ordering, packaging, and electrical specification information, see the latest plc device data sheets on the web at http://www.cypress.com . application notes cypress application notes are an excellent introduction to the wide variety of possi ble psoc designs. development kits psoc development kits are available online from and through a growing number of regional and global distributors, which include arrow, avnet, digi-key, farnell, future electronics, and newark. training free psoc technical training (on demand, webinars, and workshops), which is available online via www.cypress.com , covers a wide variety of topics an d skill levels to assist you in your designs. cypros consultants certified psoc consultants offer everything from technical assis- tance to completed psoc designs. to contact or become a psoc consultant go to the cypros consultants web site. solutions library visit our growing library of solution-focused designs . here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. technical support technical support ? including a searchable knowledge base articles and technical forums ? is also available online. if you cannot find an answer to your question, call our technical support hotline at 1-800-541-4736. CY8CPLC20 powerline network protocol physical layer fsk modem powerline communication solution powerline tran sceiver packet programmable system resources digital and analog peripherals psoc core additional system resources mac, decimator, i2c, spi, uart etc. plc core embedded application
CY8CPLC20 document number: 001-48325 rev. *j page 12 of 56 5. development tools psoc designer? is the revolutionary integrated design environment (ide) that you can use to customize psoc to meet your specific application require ments. psoc designer software accelerates system design and ti me to market. develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. then, customize your design by leveraging the dynamically generated application programming interface (api) libraries of code. finally, debug and test your designs with the integrated debug environment, incl uding in-circuit emulation and standard software debug features. psoc designer includes: application editor graphical user interface (gui) for device and user module configuration and dynamic reconfiguration extensive user module catalog integrated source-code editor (c and assembly) free c compiler with no size restrictions or time limits built-in debugger in-circuit emulation built-in support for communication interfaces: ? hardware and software i 2 c slaves and masters ? full-speed usb 2.0 ? up to four full-duplex universal asynchronous receiver/transmitters (uarts), spi master and slave, and wireless psoc designer supports the entire library of psoc 1 devices and runs on windows xp, windows vista, and windows 7. psoc designer software subsystems design entry in the chip-level view, choose a base device to work with. then select different onboard analog and digital components that use the psoc blocks, which are called user modules. examples of user modules are analog-to-digital converters (adcs), digital-to-analog converters (d acs), amplifiers, and filters. configure the user modules for your chosen application and connect them to each other and to the proper pins. then generate your project. this prepopulates your project with apis and libraries that you can use to program your application. the tool also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfiguration makes it possible to change configurations at run time. in essence, this lets you to use more than 100 percent of psoc's resources for an application. code generation tools the code generation tools work seamlessly within the psoc designer interface and have been tested with a full range of debugging tools. you can develop your design in c, assembly, or a combination of the two. assemblers . the assemblers allow you to merge assembly code seamlessly with c code. link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. c language compilers . c language compilers are available that support the psoc family of devices. the products allow you to create complete c programs for the psoc family devices. the optimizing c compilers provide all of the features of c, tailored to the psoc architecture. they come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger psoc designer has a debug environment that provides hardware in-circuit emulation, al lowing you to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow you to read and program and read and write data memory, and read and write i/o registers. you can read and write cpu registers, set and clear breakpoints, and provide program run, halt, and step control. the debugger also lets you to create a trace buffer of registers and memory locations of interest. online help system the online help system displays on line, context-sensitive help. designed for procedural and quick reference, each functional subsystem has its own context-s ensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer. in-circuit emulator a low-cost, high-functionality in-circuit emulator (ice) is available for development support. this hardware can program single devices. the emulator consists of a base unit that connects to the pc using a usb port. the base unit is universal and operates with all psoc devices. emulation pods for each device family are available separately. the emulat ion pod takes the place of the psoc device in the target board and performs full-speed (24 mhz) operation.
CY8CPLC20 document number: 001-48325 rev. *j page 13 of 56 6. designing wi th psoc designer the development process for the psoc device differs from that of a traditional fixed-function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays divi dends in managing specification change during development and lowering inventory costs. these configurable resources, called ps oc blocks, have the ability to implement a wide variety of user-selectable functions. the psoc development process is: 1. select user modules . 2. configure user modules. 3. organize and connect. 4. generate, verify, and debug. select user modules psoc designer provides a library of prebuilt, pretested hardware peripheral components called ?user modules.? user modules make selecting and implementing peripheral devices, both analog and digital, simple. configure user modules each user module that you select establishes the basic register settings that implement the select ed function. they also provide parameters and properties that allow you to tailor their precise configuration to your particular application. for example, a pwm user module configures one or more digital psoc blocks, one for each eight bits of resolution. using these parameters, you can establish the pulse width and duty cycle. configure the parameters and properties to correspond to your chosen application. enter values directly or by selecting values from drop-down menus. all of the user modules are documented in datasheets that may be viewed di rectly in psoc designer or on the cypress website. these user module datasheets explain the internal operation of the us er module and provide performance specifications. each datasheet de scribes the use of each user module parameter, and other information that you may need to successfully implement your design. organize and connect build signal chains at the chip level by interconnecting user modules to each other and the i/o pins. perform the selection, configuration, and routing so that you have complete control over all on-chip resources. generate, verify, and debug when you are ready to test the hardware configuration or move on to developing code for the project, perform the ?generate configuration files? step. this causes psoc designer to generate source code that automatic ally configures the device to your specification and provides the software for the system. the generated code provides apis with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. a complete code development environment lets you to develop and customize your applications in c, assembly language, or both. the last step in the development process takes place inside psoc designer's debugger (accessed by clicking the connect icon). psoc designer downloads the hex image to the ice where it runs at full-speed. psoc designer debugging capabil- ities rival those of systems cost ing many times more. in addition to traditional single-step, run-to -breakpoint, and watch-variable features, the debug interface provides a large trace buffer. it lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals.
CY8CPLC20 document number: 001-48325 rev. *j page 14 of 56 6.1 plc user modules powerline transceiver (plt) user module (um) enables data communication over powerlines up to baud rates of 2400 bps. this um also exposes all the apis from the network protocol for ease of application development. the um, when instantiated, provides the user with th ree implementation modes: fsk modem only ? this mode enables the user to use the raw fsk modem and build any network protocol or application with the help of the apis generated by the modem phy. fsk modem + network stack ? this mode enables the user to use the cypress network protocol for plc and build any application with the apis provi ded by the network protocol. fsk modem + network stack + i2c ? this mode enables the user to interface the CY8CPLC20 with any other microcontroller or psoc device . users can also split the application between the plc device and the external microcontroller. if the external microcontroller is a psoc device, then the i2c ums can be used to interface it with the plc device. figure 6-1 on page 14 shows the starting window for the plt um with the three implementation modes from which the user can choose. figure 6-1. plt user module the power consumption estimate of the CY8CPLC20 chip with the plt user module loaded along with the other user modules can be determined using the application note an55403 titled "est imating CY8CPLC20/cy8cled16p01 power consumption" at http://www.cypress.com . 1. pin information
CY8CPLC20 document number: 001-48325 rev. *j page 15 of 56 7. pin information the CY8CPLC20 plc device is available in a variety of packages which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital i/o. however, vss, v dd and xres are not capable of digital i/o. 7.1 28-pin part pinout notes 1. these are the issp pins, which are not high z at por (power on reset). see the psoc technical reference manual for details. 2. when using the plt user module, the extern al crystal is always required for protocol timing. for the fsk modem, either enable the pll mode or select the external 24 mhz on p1[4]. do not use the imo. table 7-1. 28-pin part pinout (ssop) pin no. type pin name description figure 7-1. CY8CPLC20 28-pin plc device digital analog 1 i/o i p0[7] analog column mux input 2 reserved rsvd reserved 3 o fsk_out analog fsk output 4 i/o i p0[1] analog column mux input 5 o tx_shutd own output to disable plc transmit circuitry in receive mode logic ?0? - when the modem is transmitting logic ?1? - when the modem is not transmitting 6 i/o p2[5] 7 i/o i p2[3] direct switched capacitor block input 8 i/o i p2[1] direct switched capacitor block input 9 reserved rsvd reserved 10 i/o p1[7] i 2 c serial clock (scl) 11 i/o p1[5] i 2 c serial data (sda) 12 i/o p1[3] xtal_stability. connect a 0.1 ? f capacitor between the pin and vss. 13 i/o p1[1] crystal (xtalin [2] ), issp-sclk [1] , i 2 c scl 14 power vss ground connection 15 i/o p1[0] crystal (xtalout [2] ), issp-sdata [1] , i 2 c sda 16 i/o p1[2] 17 i/o p1[4] optional external clock input (extclk [2] ) 18 i/o p1[6] 19 input xres active high external reset with internal pull-down 20 o rxcomp_ out analog output to external low pass filter circuitry 21 i rxcomp_ in analog input from the external low pass filter circuitry 22 analog ground agnd analog ground. connect a 1.0 f capacitor between the pin and vss. 23 i/o p2[6] external voltage reference (vref) 24 reserved rsvd reserved 25 i/o i/o p0[2] analog column mux input and column output 26 i/o i/o p0[4] analog column mux input and column output 27 i fsk_in analog fsk input 28 power v dd supply voltage legend : a = analog, i = input, o = output., rsvd = reserved (should be left unconnected) a, i, p0[7] rsvd fsk_out a, i, p0[1] tx_ shutdown p2[5] a, i, p2[3] a , i, p2[1] rsvd i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss vdd fsk_in p0[4] , a , io rsvd p2[6] , external vref agnd rxcomp_in rxcomp_ out xres p1[6] p1[4] , extclk p1[2] p1[0] , xtalout, i2c sda ssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 p0[2], a, io
CY8CPLC20 document number: 001-48325 rev. *j page 16 of 56 7.2 48-pin part pinout note 3. the qfn package has a center pad that must be connected to ground (vss). table 7-1. 48-pin part pinout (qfn ) [3] pin no. type pin name description figure 7-2. CY8CPLC20 48-pin plc device digital analog 1 i/o i p2[3] direct switched capacitor block input 2 i/o i p2[1] direct switched capacitor block input 3 i/o p4[7] 4 i/o p4[5] 5 i/o p4[3] 6 i/o p4[1] 7 reserved rsvd reserved 8 i/o p3[7] 9 i/o p3[5] 10 i/o p3[3] 11 i/o p3[1] 12 i/o p5[3] 13 i/o p5[1] 14 i/o p1[7] i 2 c serial clock (scl) 15 i/o p1[5] i 2 c serial data (sda) 16 i/o p1[3] xtal_stability. connect a 0.1 ? f capacitor between the pin and vss. 17 i/o p1[1] crystal (xtalin [2] ), i 2 c serial clock (scl), issp-sclk [1] 18 power vss ground connection 19 i/o p1[0] crystal (xtalout [2] ), i 2 c serial data (sda), issp-sdata [1] 20 i/o p1[2] 21 i/o p1[4] optional external clock input (extclk [2] ) 22 i/o p1[6] 23 i/o p5[0] 24 i/o p5[2] 25 i/o p3[0] 26 i/o p3[2] 27 i/o p3[4] 28 i/o p3[6] 29 input xres active high external reset with internal pull-down 30 i/o p4[0] 31 i/o p4[2] 32 i/o p4[4] 33 i/o p4[6] 34 orxcomp_ out analog output to external low pass filter circuitry 35 irxcomp_ in analog input from external low pass filter circuitry 36 analog ground agnd analog ground. connect a 1.0 f capacitor between the pin and vss. 37 i/o p2[6] external voltage reference (vref) 38 reserved rsvd reserved 39 i/o i/o p0[2] analog column mux input and column output 40 i/o i/o p0[4] analog column mux input and column output 41 i fsk_in analog fsk input 42 power v dd supply voltage 43 i/o i p0[7] analog column mux input 44 reserved rsvd reserved 45 o fsk_out] analog fsk output 46 i/o i p0[1] analog column mux input 47 o tx_shut down output to disable transmit circuitry in receive mode logic ?0? - when the modem is transmitting logic ?1? - when the modem is not trans- mitting 48 i/o p2[5] legend : a = analog, i = input, o = output, rsvd = reserved (should be left unconnected). qfn ( top view ) p2[5] tx_shutdown p0[1], a, i fsk_out rsvd p0[7], a, i vdd fsk_in p0[4], a, io p0[2],a,io rsvd p2[6], external vref 10 11 12 a, i, p2[3] a, i, p2[1] p4[7] p4[5] p4[3] p4[1] rsvd p3[7] p3[5] p3[3] p3[1] p5[3] 35 34 33 32 31 30 29 28 27 26 25 36 4 8 4 7 4 6 4 5 4 4 4 3 42 41 4 0 3 9 3 8 3 7 rxcomp _in rxcomp _out p4[6] p4[4] p4[2] p4[0] xres p3[6] p3[4] p3[2] p3[0] agnd 1 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 p5[1] i2c scl, p1[7] i2c sda, p1[5] p1[3] i2c scl, xtalin, p1[1] vss i2csda,xtalout,p1[0] p1[2] extclk, p1[4] p1[6] p5[0] p5[2]
CY8CPLC20 document number: 001-48325 rev. *j page 17 of 56 7.3 100-pin part pinout (on-chip debug) the 100-pin tqfp part is for the CY8CPLC20- ocd on-chip debug plc device. note that the ocd parts are only used for in-circuit debugging. ocd parts are not available for production. table 7-1. 100-pin o cd part pinout (tqfp) pin no. digital analog name description pin no. digital analog name description 1 nc no connection 51 nc no connection 2 nc no connection 52 i/o p5[0] 3 i/o i p0[1] analog column mux input 53 i/o p5[2] 4 o tx_shut down output to disable transmit circuitry in receive mode logic ?0? - when the modem is transmitting logic ?1? - when the modem is not transmitting 54 i/o p5[4] 5 i/o p2[5] 55 i/o p5[6] 6 i/o i p2[3] direct switched capacitor block input 56 i/o p3[0] 7 i/o i p2[1] direct switched capacitor block input 57 i/o p3[2] 8 i/o p4[7] 58 i/o p3[4] 9 i/o p4[5] 59 i/o p3[6] 10 i/o p4[3] 60 hclk ocd high speed clock output 11 i/o p4[1] 61 cclk ocd cpu clock output 12 ocde ocd even data i/o 62 input xres active high pin reset with internal pull-down 13 ocdo ocd odd data output 63 i/o p4[0] 14 reserved rsvd reserved 64 i/o p4[2] 15 power vss ground connection 65 power vss ground connection 16 i/o p3[7] 66 i/o p4[4] 17 i/o p3[5] 67 i/o p4[6] 18 i/o p3[3] 68 orxcomp _out analog output to external low pass filter circuitry 19 i/o p3[1] 69 irxcomp _in analog input from external low pass filter circuitry 20 i/o p5[7] 70 ground agnd analog ground. connect a 1.0 f capacitor between the pin and vss. 21 i/o p5[5] 71 nc no connection 22 i/o p5[3] 72 i/o p2[6] external voltage reference (vref) input 23 i/o p5[1] 73 nc no connection 24 i/o p1[7] i 2 c serial clock (scl) 74 reserved rsvd reserved 25 nc no connection 75 nc no connection 26 nc no connection 76 nc no connection 27 nc no connection 77 i/o i/o p0[2] analog column mux input and column output 28 i/o p1[5] i 2 c serial data (sda) 78 nc no connection 29 i/o p1[3] xtal_stability. connect a 0.1 ? f capacitor between the pin and vss. 79 i/o i/o p0[4] analog column mux input and column output, vref 30 i/o p1[1]* crystal (xtalin [2] ), i 2 c serial clock (scl), tc sclk 80 nc no connection 31 nc no connection 81 i fsk_in analog fsk input 32 power v dd supply voltage 82 power vdd supply voltage 33 nc no connection 83 power vdd supply voltage 34 power vss ground connection 84 power vss ground connection 35 nc no connection 85 power vss ground connection 36 i/o p7[7] 86 i/o p6[0] 37 i/o p7[6] 87 i/o p6[1] 38 i/o p7[5] 88 i/o p6[2] 39 i/o p7[4] 89 i/o p6[3] 40 i/o p7[3] 90 i/o p6[4] 41 i/o p7[2] 91 i/o p6[5] 42 i/o p7[1] 92 i/o p6[6] 43 i/o p7[0] 93 i/o p6[7] 44 i/o p1[0]* crystal (xtalout [2] ), i 2 c serial data (sda), tc sdata 94 nc no connection 45 i/o p1[2] 95 i/o i p0[7] analog column mux input 46 i/o p1[4] optional external clock input (extclk [2] ) 96 nc no connection 47 i/o p1[6] 97 reserved rsvd reserved 48 nc no connection 98 nc no connection 49 nc no connection 99 o fsk_out analog fsk output 50 nc no connection 100 nc no connection legend a = analog, i = input, o = output, nc = no connection, tc /tm: test, rsvd = reserved (should be left unconnected).
CY8CPLC20 document number: 001-48325 rev. *j page 18 of 56 figure 7-3. CY8CPLC20-ocd not for production ocd tqfp 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 nc nc ai , p0[1] tx_ shutdown p2[5] ai , p2[3] ai , p2[1] p4[7] p4[5] p4[3] p4[1] ocde ocdo rsvd vss p3[7] p3[5] p3[3] p3[1] p5[7] p5[5] p5[3] p5[1] i2 c scl, p1[7] nc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 49 nc vss p7[3] extclk, p1[4] nc i2c sda, p1[5] p1[3] xtalin, i2c scl, p1[1] nc vdd nc nc p7[7] p7[6] p7[5] p7[4] p7[2] p7[1] p7[0] xtalout, i2c sda, p1[0] p1[2] p1[6] nc nc nc 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc rsvd nc p2[6] , external vref nc agnd rxcomp _in rxcomp _out p4[6] p4[4] vss p4[2] p4[0] xres cclk hclk p3[6] p3[4] p3[2] p3[0] p5[6] p5[4] p5[2] p5[0] nc nc fsk_out nc rsvd nc p0[7], ai nc p6[7] p6[6] p6[5] p6[4] p6[3] p6[2] p6[1] p6[0] vss vss vdd vdd fsk_in nc p0[4], aio nc p0[2]. a, io nc
CY8CPLC20 document number: 001-48325 rev. *j page 19 of 56 8. register reference this section lists the registers of the CY8CPLC20 plc device. for detailed register information, reference the plc technical reference manual . 8.1 register conventions 8.1.1 abbreviations used the register conventions specific to this section are listed in the following table. 8.2 register mapping tables the CY8CPLC20 device has a total register address space of 512 bytes. the register space is referred to as i/o space and is divided into two banks, bank 0 a nd bank 1. the xoi bit in the flag register (cpu_f) determines which bank the user is currently in. when the xoi bit is set the user is in bank 1. note in the following register mapping tables, blank fields are reserved and should not be accessed. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
CY8CPLC20 document number: 001-48325 rev. *j page 20 of 56 table 8-1. register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw dbb20dr0 40 # asc10cr0 80 rw rdi2ri c0 rw prt0ie 01 rw dbb20dr1 41 w asc10cr1 81 rw rdi2syn c1 rw prt0gs 02 rw dbb20dr2 42 rw asc10cr2 82 rw rdi2is c2 rw prt0dm2 03 rw dbb20cr0 43 # asc10cr3 83 rw rdi2lt0 c3 rw prt1dr 04 rw dbb21dr0 44 # asd11cr0 84 rw rdi2lt1 c4 rw prt1ie 05 rw dbb21dr1 45 w asd11cr1 85 rw rdi2ro0 c5 rw prt1gs 06 rw dbb21dr2 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1dm2 07 rw dbb21cr0 47 # asd11cr3 87 rw c7 prt2dr 08 rw dcb22dr0 48 # asc12cr0 88 rw rdi3ri c8 rw prt2ie 09 rw dcb22dr1 49 w asc12cr1 89 rw rdi3syn c9 rw prt2gs 0a rw dcb22dr2 4a rw asc12cr2 8a rw rdi3is ca rw prt2dm2 0b rw dcb22cr0 4b # asc12cr3 8b rw rdi3lt0 cb rw prt3dr 0c rw dcb23dr0 4c # asd13cr0 8c rw rdi3lt1 cc rw prt3ie 0d rw dcb23dr1 4d w asd13cr1 8d rw rdi3ro0 cd rw prt3gs 0e rw dcb23dr2 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3dm2 0f rw dcb23cr0 4f # asd13cr3 8f rw cf prt4dr 10 rw dbb30dr0 50 # asd20cr0 90 rw cur_pp d0 rw prt4ie 11 rw dbb30dr1 51 w asd20cr1 91 rw stk_pp d1 rw prt4gs 12 rw dbb30dr2 52 rw asd20cr2 92 rw d2 prt4dm2 13 rw dbb30cr0 53 # asd20cr3 93 rw idx_pp d3 rw prt5dr 14 rw dbb31dr0 54 # asc21cr0 94 rw mvr_pp d4 rw prt5ie 15 rw dbb31dr1 55 w asc21cr1 95 rw mvw_pp d5 rw prt5gs 16 rw dbb31dr2 56 rw asc21cr2 96 rw i2c_cfg d6 rw prt5dm2 17 rw dbb31cr0 57 # asc21cr3 97 rw i2c_scr d7 # prt6dr 18 rw dcb32dr0 58 # asd22cr0 98 rw i2c_dr d8 rw prt6ie 19 rw dcb32dr1 59 w asd22cr1 99 rw i2c_mscr d9 # prt6gs 1a rw dcb32dr2 5a rw asd22cr2 9a rw int_clr0 da rw prt6dm2 1b rw dcb32cr0 5b # asd22cr3 9b rw int_clr1 db rw prt7dr 1c rw dcb33dr0 5c # asc23cr0 9c rw int_clr2 dc rw prt7ie 1d rw dcb33dr1 5d w asc23cr1 9d rw int_clr3 dd rw prt7gs 1e rw dcb33dr2 5e rw asc23cr2 9e rw int_msk3 de rw prt7dm2 1f rw dcb33cr0 5f # asc23cr3 9f rw int_msk2 df rw dbb00dr0 20 # amx_in 60 rw a0 int_msk0 e0 rw dbb00dr1 21 w 61 a1 int_msk1 e1 rw dbb00dr2 22 rw 62 a2 int_vc e2 rc dbb00cr0 23 # arf_cr 63 rw a3 res_wdt e3 w dbb01dr0 24 # cmp_cr0 64 # a4 dec_dh e4 rc dbb01dr1 25 w asy_cr 65 # a5 dec_dl e5 rc dbb01dr2 26 rw cmp_cr1 66 rw a6 dec_cr0 e6 rw dbb01cr0 27 # 67 a7 dec_cr1 e7 rw dcb02dr0 28 # 68 mul1_x a8 w mul0_x e8 w dcb02dr1 29 w 69 mul1_y a9 w mul0_y e9 w dcb02dr2 2a rw 6a mul1_dh aa r mul0_dh ea r dcb02cr0 2b # 6b mul1_dl ab r mul0_dl eb r dcb03dr0 2c # tmp_dr0 6c rw acc1_dr1 ac rw acc0_dr1 ec rw dcb03dr1 2d w tmp_dr1 6d rw acc1_dr0 ad rw acc0_dr0 ed rw dcb03dr2 2e rw tmp_dr2 6e rw acc1_dr3 ae rw acc0_dr3 ee rw dcb03cr0 2f # tmp_dr3 6f rw acc1_dr2 af rw acc0_dr2 ef rw dbb10dr0 30 # acb00cr3 70 rw rdi0ri b0 rw f0 dbb10dr1 31 w acb00cr0 71 rw rdi0syn b1 rw f1 dbb10dr2 32 rw acb00cr1 72 rw rdi0is b2 rw f2 dbb10cr0 33 # acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11dr0 34 # acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11dr1 35 w acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11dr2 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 dbb11cr0 37 # acb01cr2 77 rw b7 cpu_f f7 rl dcb12dr0 38 # acb02cr3 78 rw rdi1ri b8 rw f8 dcb12dr1 39 w acb02cr0 79 rw rdi1syn b9 rw f9 dcb12dr2 3a rw acb02cr1 7a rw rdi1is ba rw fa dcb12cr0 3b # acb02cr2 7b rw rdi1lt0 bb rw fb dcb13dr0 3c # acb03cr3 7c rw rdi1lt1 bc rw fc dcb13dr1 3d w acb03cr0 7d rw rdi1ro0 bd rw fd dcb13dr2 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # dcb13cr0 3f # acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should no t be accessed. # access is bit specific.
CY8CPLC20 document number: 001-48325 rev. *j page 21 of 56 table 8-2. register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw dbb20fn 40 rw asc10cr0 80 rw rdi2ri c0 rw prt0dm1 01 rw dbb20in 41 rw asc10cr1 81 rw rdi2syn c1 rw prt0ic0 02 rw dbb20ou 42 rw asc10cr2 82 rw rdi2is c2 rw prt0ic1 03 rw 43 asc10cr3 83 rw rdi2lt0 c3 rw prt1dm0 04 rw dbb21fn 44 rw asd11cr0 84 rw rdi2lt1 c4 rw prt1dm1 05 rw dbb21in 45 rw asd11cr1 85 rw rdi2ro0 c5 rw prt1ic0 06 rw dbb21ou 46 rw asd11cr2 86 rw rdi2ro1 c6 rw prt1ic1 07 rw 47 asd11cr3 87 rw c7 prt2dm0 08 rw dcb22fn 48 rw asc12cr0 88 rw rdi3ri c8 rw prt2dm1 09 rw dcb22in 49 rw asc12cr1 89 rw rdi3syn c9 rw prt2ic0 0a rw dcb22ou 4a rw asc12cr2 8a rw rdi3is ca rw prt2ic1 0b rw 4b asc12cr3 8b rw rdi3lt0 cb rw prt3dm0 0c rw dcb23fn 4c rw asd13cr0 8c rw rdi3lt1 cc rw prt3dm1 0d rw dcb23in 4d rw asd13cr1 8d rw rdi3ro0 cd rw prt3ic0 0e rw dcb23ou 4e rw asd13cr2 8e rw rdi3ro1 ce rw prt3ic1 0f rw 4f asd13cr3 8f rw cf prt4dm0 10 rw dbb30fn 50 rw asd20cr0 90 rw gdi_o_in d0 rw prt4dm1 11 rw dbb30in 51 rw asd20cr1 91 rw gdi_e_in d1 rw prt4ic0 12 rw dbb30ou 52 rw asd20cr2 92 rw gdi_o_ou d2 rw prt4ic1 13 rw 53 asd20cr3 93 rw gdi_e_ou d3 rw prt5dm0 14 rw dbb31fn 54 rw asc21cr0 94 rw d4 prt5dm1 15 rw dbb31in 55 rw asc21cr1 95 rw d5 prt5ic0 16 rw dbb31ou 56 rw asc21cr2 96 rw d6 prt5ic1 17 rw 57 asc21cr3 97 rw d7 prt6dm0 18 rw dcb32fn 58 rw asd22cr0 98 rw d8 prt6dm1 19 rw dcb32in 59 rw asd22cr1 99 rw d9 prt6ic0 1a rw dcb32ou 5a rw asd22cr2 9a rw da prt6ic1 1b rw 5b asd22cr3 9b rw db prt7dm0 1c rw dcb33fn 5c rw asc23cr0 9c rw dc prt7dm1 1d rw dcb33in 5d rw asc23cr1 9d rw osc_go_en dd rw prt7ic0 1e rw dcb33ou 5e rw asc23cr2 9e rw osc_cr4 de rw prt7ic1 1f rw 5f asc23cr3 9f rw osc_cr3 df rw dbb00fn 20 rw clk_cr0 60 rw a0 osc_cr0 e0 rw dbb00in 21 rw clk_cr1 61 rw a1 osc_cr1 e1 rw dbb00ou 22 rw abf_cr0 62 rw a2 osc_cr2 e2 rw 23 amd_cr0 63 rw a3 vlt_cr e3 rw dbb01fn 24 rw 64 a4 vlt_cmp e4 r dbb01in 25 rw 65 a5 e5 dbb01ou 26 rw amd_cr1 66 rw a6 e6 27 alt_cr0 67 rw a7 dec_cr2 e7 rw dcb02fn 28 rw alt_cr1 68 rw a8 imo_tr e8 w dcb02in 29 rw clk_cr2 69 rw a9 ilo_tr e9 w dcb02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eco_tr eb w dcb03fn 2c rw tmp_dr0 6c rw ac ec dcb03in 2d rw tmp_dr1 6d rw ad ed dcb03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef dbb10fn 30 rw acb00cr3 70 rw rdi0ri b0 rw f0 dbb10in 31 rw acb00cr0 71 rw rdi0syn b1 rw f1 dbb10ou 32 rw acb00cr1 72 rw rdi0is b2 rw f2 33 acb00cr2 73 rw rdi0lt0 b3 rw f3 dbb11fn 34 rw acb01cr3 74 rw rdi0lt1 b4 rw f4 dbb11in 35 rw acb01cr0 75 rw rdi0ro0 b5 rw f5 dbb11ou 36 rw acb01cr1 76 rw rdi0ro1 b6 rw f6 37 acb01cr2 77 rw b7 cpu_f f7 rl dcb12fn 38 rw acb02cr3 78 rw rdi1ri b8 rw f8 dcb12in 39 rw acb02cr0 79 rw rdi1syn b9 rw f9 dcb12ou 3a rw acb02cr1 7a rw rdi1is ba rw fls_pr1 fa rw 3b acb02cr2 7b rw rdi1lt0 bb rw fb dcb13fn 3c rw acb03cr3 7c rw rdi1lt1 bc rw fc dcb13in 3d rw acb03cr0 7d rw rdi1ro0 bd rw fd dcb13ou 3e rw acb03cr1 7e rw rdi1ro1 be rw cpu_scr1 fe # 3f acb03cr2 7f rw bf cpu_scr0 ff # blank fields are reserved and should not be accessed. # access is bit specific.
CY8CPLC20 document number: 001-48325 rev. *j page 22 of 56 9. electrica l specifications this section presents the dc and ac electrical specifications of the CY8CPLC20 device. for the most up-to-date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. specifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. 9.1 absolute maximum ratings exceeding maximum ratings may shorten the useful li fe of the device. user guidelines are not tested. 9.2 operating temperature table 9-1. absolute maximum ratings symbol description min typ max units notes t stg storage temperature ?55 25 +100 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 ? c 25 ? c. extended duration storage temperatures above 65 ? c degrade reliability. t baketemp bake temperature ? 125 see package label ? c t baketime bake time see package label ? 72 hours t a ambient temperature with power applied ?40 ? +85 c v dd supply voltage on v dd relative to vss ?0.5 ? +6.0 v v io dc input voltage v ss - 0.5 ? v dd + 0.5 v v ioz dc voltage applied to tri-state v ss - 0.5 ? v dd + 0.5 v i mio maximum current into any port pin ?25 ? +50 ma i maio maximum current into any port pin configured as analog driver ?50 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 9-2. operating temperature symbol description min typ max units notes t a ambient temperature ?40 ? +85 ? c t j junction temperature ?40 ? +100 ? c the temperature rise from ambient to junction is package specific. see thermal imped- ances on page 44 .the user must limit the power consumption to comply with this requirement.
CY8CPLC20 document number: 001-48325 rev. *j page 23 of 56 9.3 dc electrical characteristics 9.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. 9.3.2 dc gpio specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temper ature range: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. table 9-3. dc chip-level specifications symbol description min typ max units notes v dd supply voltage 4.75 ? 5.25 v i dd supply current ? 8 14 ma conditions are 5.0 v, t a = 25 ? c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 0.366 khz v ref reference voltage (bandgap) 1.28 1.3 1.32 v trimmed for appropriate v dd table 9-4. dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? r pd pull-down resistor 4 5.6 8 k ? v oh high output level v dd - 1.0 ? ? v ioh = 10 ma, (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 80 ma maximum combined ioh budget. v ol low output level ? ? 0.75 v iol = 25 ma , (8 total loads, 4 on even port pins (for example, p0[2], p1[4]), 4 on odd port pins (for example, p0[3], p1[5])). 150 ma maximum combined iol budget. i oh high level source current 10 ? ? ma voh = v dd -1.0 v. see the limitations of the total current in the note for voh. i ol low level sink current 25 ? ? ma vol = 0.75 v. see the limitations of the total current in the note for vol. v il input low level ? ? 0.8 v v ih input high level 2.1 ? v v h input hysterisis ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 ? a. c in capacitive load on pins as input ? 3.5 10 pf package and pin dependent. temp = 25 ? c. c out capacitive load on pins as output ? 3.5 10 pf package and pin dependent. temp = 25 ? c.
CY8CPLC20 document number: 001-48325 rev. *j page 24 of 56 9.3.3 dc operational am plifier specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 c and are for design guidance only. the operational amplifier is a component of both the analog continuous time psoc blocks and the analog switched capacitor psoc blocks. the guaranteed specifications are measured in the analog continuous time pso c block. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. 9.3.4 dc low power comp arator specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 c ? t a ? 85 c. typical parameters are measured at 5 v at 25 c and are for design guidance only. table 9-5. 5-v dc operational amplifier specifications symbol description min typ max unit notes v osoa input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 1.6 1.6 1.6 1.6 1.6 1.6 10 10 10 10 10 10 mv mv mv mv mv mv tcv osoa average input offset voltage drift ? 4 23 v/c i eboa input leakage current (port 0 analog pins) ? 200 ? pa gross tested to 1 a c inoa input capacitance (port 0 analog pins) ? 4.5 9.5 pf package and pin dependent. te m p = 2 5 c v cmoa common mode voltage range (all cases, except power = high, opamp bias = high) common mode voltage range (power = high, opamp bias = high) 0 0.5 ? ? v dd v dd ? 0.5 v v the common-mode input voltage range is measured through an analog output buffer. the specification includes the limitations imposed by the characteristics of the analog output buffer. cmrroa common mode rejection ratio 60 ? ? db goloa open loop gain 80 ? ? db v ohighoa high output voltage swing (internal signals) v dd ? 0.01 ? ? v v olowoa low output voltage swing (internal signals) ? ? 0.1 v i soa supply current (including associated agnd buffer) power = low, opamp bias = low power = low, opamp bias = high power = medium, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? ? ? 150 300 600 1200 2400 4600 200 400 800 1600 3200 6400 a a a a a a psrr oa supply voltage rejection ratio 67 80 ? db v ss ? v in ? (v dd ? 2.25) or (v dd ? 1.25 v) ? v in ? v dd . table 9-6. dc low power comparator specifications symbol description min typ max units notes v reflpc low power comparator (lpc) reference voltage range 0.2 ? v dd - 1 v i slpc lpc supply current ? 10 40 ? a v oslpc lpc voltage offset ? 2.5 30 mv
CY8CPLC20 document number: 001-48325 rev. *j page 25 of 56 9.3.5 dc analog output buffer specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. table 9-7. dc analog output buffer specifications symbol description min typ max units notes c l load capacitance ? ? 200 pf this specification applies to the external circuit driven by the analog output buffer. v osob input offset voltage (absolute value) power = low, opamp bias = low power = low, opamp bias = high power = high, opamp bias = low power = high, opamp bias = high ? ? ? ? 3.2 3.2 3.2 3.2 18 18 18 18 mv mv mv mv tcv osob average input offset voltage drift ? 5.5 26 ? v/ ? c v cmob common-mode input voltage range 0.5 ? v dd ? 1.0 v r outob output resistance power = low power = high ? ? ? ? 1 1 w w v ohighob high output voltage swing (load = 32 ohms to v dd /2) power = low power = high 0.5 x v dd + 1.3 0.5 x v dd + 1.3 ? ? ? ? v v v olowob low output voltage swing (load = 32 ohms to v dd /2) power = low power = high ? ? ? ? 0.5 x v dd - 1.3 0.5 x v dd - 1.3 v v i sob supply current including bias cell (no load) power = low power = high ? ? 1.1 2.6 2 5 ma ma psrr ob supply voltage rejection ratio 40 64 ? db
CY8CPLC20 document number: 001-48325 rev. *j page 26 of 56 9.3.6 dc analog reference specifications ta b l e 9 - 8 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. the guaranteed specificat ions are measured through the anal og continuous time psoc blocks. the power levels for agnd refer to the power of the analog continuous time psoc block. the power leve ls for refhi and reflo refer to the analog reference control register. the limits stated for agnd include the offset error of the agnd buffer local to the analog continuous time psoc block . reference control power is high. note avoid using p2[4] for digital signaling when using an analog reso urce that depends on the analog reference. some coupling of the digital signal may appear on the agnd. table 9-8. 5-v dc analog reference specifications reference arf_cr[5:3] reference power settings symbol reference description min typ max unit 0b000 refpower = high opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.228 v dd /2 + 1.290 v dd /2 + 1.352 v v agnd agnd v dd /2 v dd /2 ? 0.078 v dd /2 ? 0.007 v dd /2 + 0.063 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.336 v dd /2 ? 1.295 v dd /2 ? 1.250 v refpower = high opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.224 v dd /2 + 1.293 v dd /2 + 1.356 v v agnd agnd v dd /2 v dd /2 ? 0.056 v dd /2 ? 0.005 v dd /2 + 0.043 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.338 v dd /2 ? 1.298 v dd /2 ? 1.255 v refpower = med opamp bias = high v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.293 v dd /2 + 1.356 v v agnd agnd v dd /2 v dd /2 ? 0.057 v dd /2 ? 0.006 v dd /2 + 0.044 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.337 v dd /2 ? 1.298 v dd /2 ? 1.256 v refpower = med opamp bias = low v refhi ref high v dd /2 + bandgap v dd /2 + 1.226 v dd /2 + 1.294 v dd /2 + 1.359 v v agnd agnd v dd /2 v dd /2 ? 0.047 v dd /2 ? 0.004 v dd /2 + 0.035 v v reflo ref low v dd /2 ? bandgap v dd /2 ? 1.338 v dd /2 ? 1.299 v dd /2 ? 1.258 v
CY8CPLC20 document number: 001-48325 rev. *j page 27 of 56 0b001 refpower = high opamp bias = high v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.085 p2[4] + p2[6] ? 0.016 p2[4] + p2[6] + 0.044 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.010 p2[4] ? p2[6] + 0.055 v refpower = high opamp bias = low v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.077 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.051 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.039 v refpower = med opamp bias = high v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.010 p2[4] + p2[6] + 0.050 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.005 p2[4] ? p2[6] + 0.039 v refpower = med opamp bias = low v refhi ref high p2[4] + p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] + p2[6] ? 0.070 p2[4] + p2[6] ? 0.007 p2[4] + p2[6] + 0.054 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? p2[6] (p2[4] = v dd /2, p2[6] = 1.3 v) p2[4] ? p2[6] ? 0.022 p2[4] ? p2[6] + 0.002 p2[4] ? p2[6] + 0.032 v 0b010 refpower = high opamp bias = high v refhi ref high v dd v dd ? 0.037 v dd ? 0.009 v dd v v agnd agnd v dd /2 v dd /2 ? 0.061 v dd /2 ? 0.006 v dd /2 + 0.047 v v reflo ref low v ss v ss v ss + 0.007 v ss + 0.028 v refpower = high opamp bias = low v refhi ref high v dd v dd ? 0.039 v dd ? 0.006 v dd v v agnd agnd v dd /2 v dd /2 ? 0.049 v dd /2 ? 0.005 v dd /2 + 0.036 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.019 v refpower = med opamp bias = high v refhi ref high v dd v dd ? 0.037 v dd ? 0.007 v dd v v agnd agnd v dd /2 v dd /2 ? 0.054 v dd /2 ? 0.005 v dd /2 + 0.041 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.024 v refpower = med opamp bias = low v refhi ref high v dd v dd ? 0.042 v dd ? 0.005 v dd v v agnd agnd v dd /2 v dd /2 ? 0.046 v dd /2 ? 0.004 v dd /2 + 0.034 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.017 v table 9-8. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit
CY8CPLC20 document number: 001-48325 rev. *j page 28 of 56 0b011 refpower = high opamp bias = high v refhi ref high 3 bandgap 3.788 3.891 3.986 v v agnd agnd 2 bandgap 2.500 2.604 3.699 v v reflo ref low bandgap 1.257 1.306 1.359 v refpower = high opamp bias = low v refhi ref high 3 bandgap 3.792 3.893 3.982 v v agnd agnd 2 bandgap 2.518 2.602 2.692 v v reflo ref low bandgap 1.256 1.302 1.354 v refpower = med opamp bias = high v refhi ref high 3 bandgap 3.795 3.894 3.993 v v agnd agnd 2 bandgap 2.516 2.603 2.698 v v reflo ref low bandgap 1.256 1.303 1.353 v refpower = med opamp bias = low v refhi ref high 3 bandgap 3.792 3.895 3.986 v v agnd agnd 2 bandgap 2.522 2.602 2.685 v v reflo ref low bandgap 1.255 1.301 1.350 v 0b100 refpower = high opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.495 ? p2[6] 2.586 ? p2[6] 2.657 ? p2[6] v v agnd agnd 2 bandgap 2.502 2.604 2.719 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.531 ? p2[6] 2.611 ? p2[6] 2.681 ? p2[6] v refpower = high opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.500 ? p2[6] 2.591 ? p2[6] 2.662 ? p2[6] v v agnd agnd 2 bandgap 2.519 2.602 2.693 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.530 ? p2[6] 2.605 ? p2[6] 2.666 ? p2[6] v refpower = med opamp bias = high v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.503 ? p2[6] 2.592 ? p2[6] 2.662 ? p2[6] v v agnd agnd 2 bandgap 2.517 2.603 2.698 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.529 ? p2[6] 2.606 ? p2[6] 2.665 ? p2[6] v refpower = med opamp bias = low v refhi ref high 2 bandgap + p2[6] (p2[6] = 1.3 v) 2.505 ? p2[6] 2.594 ? p2[6] 2.665 ? p2[6] v v agnd agnd 2 bandgap 2.525 2.602 2.685 v v reflo ref low 2 bandgap ? p2[6] (p2[6] = 1.3 v) 2.528 ? p2[6] 2.603 ? p2[6] 2.661 ? p2[6] v table 9-8. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit
CY8CPLC20 document number: 001-48325 rev. *j page 29 of 56 0b101 refpower = high opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.222 p2[4] + 1.290 p2[4] + 1.343 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.295 p2[4] ? 1.254 v refpower = high opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.226 p2[4] + 1.293 p2[4] + 1.347 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.298 p2[4] ? 1.259 v refpower = med opamp bias = high v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.227 p2[4] + 1.294 p2[4] + 1.347 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.331 p2[4] ? 1.298 p2[4] ? 1.259 v refpower = med opamp bias = low v refhi ref high p2[4] + bandgap (p2[4] = v dd /2) p2[4] + 1.228 p2[4] + 1.295 p2[4] + 1.349 v v agnd agnd p2[4] p2[4] p2[4] p2[4] ? v reflo ref low p2[4] ? bandgap (p2[4] = v dd /2) p2[4] ? 1.332 p2[4] ? 1.299 p2[4] ? 1.260 v 0b110 refpower = high opamp bias = high v refhi ref high 2 bandgap 2.535 2.598 2.644 v v agnd agnd bandgap 1.227 1.305 1.398 v v reflo ref low v ss v ss v ss + 0.009 v ss + 0.038 v refpower = high opamp bias = low v refhi ref high 2 bandgap 2.530 2.598 2.643 v v agnd agnd bandgap 1.244 1.303 1.370 v v reflo ref low v ss v ss v ss + 0.005 v ss + 0.024 v refpower = med opamp bias = high v refhi ref high 2 bandgap 2.532 2.598 2.644 v v agnd agnd bandgap 1.239 1.304 1.380 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.026 v refpower = med opamp bias = low v refhi ref high 2 bandgap 2.528 2.598 2.645 v v agnd agnd bandgap 1.249 1.302 1.362 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.018 v 0b111 refpower = high opamp bias = high v refhi ref high 3.2 bandgap 4.041 4.155 4.234 v v agnd agnd 1.6 bandgap 1.998 2.083 2.183 v v reflo ref low v ss v ss v ss + 0.010 v ss + 0.038 v refpower = high opamp bias = low v refhi ref high 3.2 bandgap 4.047 4.153 4.236 v v agnd agnd 1.6 bandgap 2.012 2.082 2.157 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.024 v refpower = med opamp bias = high v refhi ref high 3.2 bandgap 4.049 4.154 4.238 v v agnd agnd 1.6 bandgap 2.008 2.083 2.165 v v reflo ref low v ss v ss v ss + 0.006 v ss + 0.026 v refpower = med opamp bias = low v refhi ref high 3.2 bandgap 4.047 4.154 4.238 v v agnd agnd 1.6 bandgap 2.016 2.081 2.150 v v reflo ref low v ss v ss v ss + 0.004 v ss + 0.018 v table 9-8. 5-v dc analog reference specifications (continued) reference arf_cr[5:3] reference power settings symbol reference description min typ max unit
CY8CPLC20 document number: 001-48325 rev. *j page 30 of 56 9.3.7 dc analog psoc block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ?? c and are for design guidance only. 9.3.8 por and lvd specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. table 9-9. dc analog psoc block specifications symbol description min typ max units notes r ct resistor unit value (continuous time) ? 12.2 ? k ? c sc capacitor unit value (switch cap) ? 80 ? ff table 9-10. dc por and lvd specifications symbol description min typ max units notes v ppor2r vdd value for ppor trip (positive ramp) porlev[1:0] = 10b ? 4.55 ? v v ppor2 v dd value for ppor trip (negative ramp) porlev[1:0] = 10b ? 4.55 ? v v ph2 ppor hysteresis porlev[1:0] = 10b ? 0 ? mv v lvd6 v lvd7 v dd value for lvd trip vm[2:0] = 110b vm[2:0] = 111b 4.63 4.72 4.73 4.81 4.82 4.91 v v
CY8CPLC20 document number: 001-48325 rev. *j page 31 of 56 9.3.9 dc programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. dc i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. notes 4. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles eac h (to limit the total number of cycles to 36x5 0,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperat ure sensor user module (flash temp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. 5. all gpios meet the dc gpio v il and v ih specifications found in the dc gpio specifications sections.the i 2 c gpio pins also meet the mentioned specs. table 9-11. dc programming specifications symbol description min typ max units notes v ddp v dd for programming and erase 4.5 5 5.5 v this specification applies to the functional requirements of external programmer tools. v ddlv low v dd for verify 4.7 4.8 4.9 v this specification applies to the functional requirements of external programmer tools. v ddhv high v dd for verify 5.1 5.2 5.3 v this specification applies to the functional requirements of external programmer tools. v ddiwrite supply voltage for flash write operation 4.75 5,0 5.25 v this specification applies to this device when it is executing internal flash writes. i ddp supply current during programming or verify ? 10 30 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying v ilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor i ihp input current when applying v ihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify v dd - 1.0 ? v dd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block flash ent flash endurance (total) [4] 1,800,000 ? ? ? erase/write cycles flash dr flash data retention 10 ? ? years table 9-12. dc i 2 c specifications parameter description min typ max units notes v ili2c [5] input low level ? ? 0.25 v dd v4.75 v ? v dd ?? 5.25 v v ihi2c [5] input high level 0.7 v dd ?? v4.75 v ?? v dd ?? 5.25 v
CY8CPLC20 document number: 001-48325 rev. *j page 32 of 56 9.4 ac electrical characteristics 9.4.1 ac chip-level specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ?? c and are for design guidance only. note see the individual user module data sheets for information on maximum frequencies for user modules. table 9-13. ac chip-level specifications symbol description min typ max units notes f imo24 internal main oscillator frequency for 24 mhz 23.4 24 24.6 mhz trimmed for 5v operation using factory trim values. slimo mode = 0. f imo6 internal main oscillator frequency for 6 mhz 5.5 6 6.5 [6] mhz trimmed for 5v operation using factory trim values. slimo mode = 1. f cpu1 cpu frequency (5 v nominal) 0.0914 24 24.6 [6] mhz slimo mode = 0. f 48m digital psoc block frequency 0 48 49.2 [6, 7] mhz refer to the ac digital block specifications below. f 32k1 internal low speed oscillator frequency 15 32 64 khz f 32k2 external crystal oscillator ? 32.768 ? khz accuracy is capacitor and crystal dependent. 50% duty cycle. f 32k_u internal low speed oscillator (ilo) untrimmed frequency 5 ? 100 khz after a reset and before the m8c starts to run, the ilo is not trimmed. see the system resets section of the psoc technical reference manual for details on this timing. f pll pll frequency ? 23.986 ? mhz a multiple (x732) of crystal frequency. t pllslew pll lock time 0.5 ? 10 ms t pllslewlow pll lock time for low gain setting 0.5 ? 50 ms t os external crystal oscillator startup to 1% ? 250 500 ms t osacc external crystal oscillator startup to 100 ppm ? 300 600 ms the crystal oscillator frequency is within 100 ppm of its final value by the end of the t osacc period. correct operation assumes a properly loaded 1 ? w maximum drive level 32.768 khz crystal. ?40 ? c ? t a ? 85 ? c. t xrst external reset pulse width 10 ? ? ? s sr power_up power supply slew rate ? ? 250 v/ms v dd slew rate during power up. t powerup time from end of por to cpu executing code ? 16 100 ms power up from 0 v. see the system resets section of the p soc technical reference manual . dc24m 24 mhz duty cycle 40 50 60 % dc ilo internal low speed oscillator duty cycle 20 50 80 % step24m 24 mhz trim step size ? 50 ? khz fout48m 48 mhz output frequency 46.8 48.0 49.2 mhz trimmed. utilizing factory trim values. f max maximum frequency of signal on row input or row output. ? ? 12.3 mhz notes 6. accuracy derived from internal main oscillator with appropriate trim for vdd range. 7. see the individual user module data sheets for in formation on maximum frequencies for user modules. 8. refer to cypress jitter specifications application note, understanding datasheet jitter specificat ions for cypress timing products ? an5054 for more information.
CY8CPLC20 document number: 001-48325 rev. *j page 33 of 56 figure 9-1. pll lock timing diagram figure 9-2. pll lock for low gain setting timing diagram figure 9-3. external crystal o scillator startup timing diagram t jit_imo [8] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 700 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 900 ps n = 32 24 mhz imo period jitter (rms) ? 100 400 ps t jit_pll [8] 24 mhz imo cycle-to-cycle jitter (rms) ? 200 800 ps 24 mhz imo long term n cycle-to-cycle jitter (rms) ? 300 1200 ps n = 32 24 mhz imo period jitter (rms) ? 100 700 ps table 9-13. ac chip-level specifications (continued) symbol description min typ max units notes 24 mhz f pll pll enable t pllslew pll gain 0 24 mhz f pll pll enable t pllslewlow pll gain 1 32 khz f 32k2 32k select t os
CY8CPLC20 document number: 001-48325 rev. *j page 34 of 56 9.4.2 ac gpio specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. figure 9-4. gpio timing diagram table 9-1. ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 12.3 mhz normal strong mode trisef rise time, normal strong mode, cload = 50 pf 3 ? 18 ns 10% to 90% tfallf fall time, normal strong mode, cload = 50 pf 2 ? 18 ns 10% to 90% trises rise time, slow strong mode, cload = 50 pf 10 27 ? ns 10% to 90% tfalls fall time, slow strong mode, cload = 50 pf 10 22 ? ns 10% to 90% tfallf tfalls tris ef trises 90% 10% gpio pin output voltage
CY8CPLC20 document number: 001-48325 rev. *j page 35 of 56 9.4.3 ac operational amplifier specifications ta b l e 9 - 1 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. settling times, slew rates, and gain bandwidth are based on the analog continuous time psoc block. table 9-1. 5v ac operational amplifier specifications symbol description min typ max units notes t roa rising settling time to 0.1% for a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 3.9 0.72 0.62 ? s ? s ? s t soa falling settling time to 0.1% for a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high ? ? ? ? ? ? 5.9 0.92 0.72 ? s ? s ? s sr roa rising slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.15 1.7 6.5 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s sr foa falling slew rate (20% to 80%) of a 1 v step (10 pf load, unity gain) power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.01 0.5 4.0 ? ? ? ? ? ? v/ ? s v/ ? s v/ ? s bw oa gain bandwidth product power = low, opamp bias = low power = medium, opamp bias = high power = high, opamp bias = high 0.75 3.1 5.4 ? ? ? ? ? ? mhz mhz mhz e noa noise at 1 khz (power = medium, opamp bias = high) ? 100 ? nv/rt-hz
CY8CPLC20 document number: 001-48325 rev. *j page 36 of 56 when bypassed by a capacitor on p2[4], the noise of the analog ground signal distributed to each bl ock is reduced by a factor o f up to 5 (14 db). this is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacit or. figure 9-5. typical agnd noise with p2[4] bypass at low frequencies, the opamp noise is proportional to 1/ f, power independent, and determined by device geometry. at high frequencies, increased power level reduces the noise spectrum level. figure 9-6. typical opamp noise 9.4.3 ac low power comparator specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ?? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. ? table 9-1. ac low power comparator specifications symbol description min typ max units notes t rlpc lpc response time ? ? 50 ? s ? 50 mv overdrive comparator reference set within v reflpc .
CY8CPLC20 document number: 001-48325 rev. *j page 37 of 56 9.4.4 ac digital block specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. table 9-2. ac digital block specifications function description min typ max unit notes all functions block input clock frequency v dd ? 4.75 v ? ? 49.2 mhz timer input clock frequency no capture, v dd ?? 4.75 v ? ? 49.2 mhz with capture ? ? 24.6 mhz capture pulse width 50 [9] ??ns counter input clock frequency no enable input, v dd ? 4.75 v ? ? 49.2 mhz with enable input ? ? 24.6 mhz enable input pulse width 50 [9] ??ns dead band kill pulse width asynchronous restart mode 20 ? ? ns synchronous restart mode 50 [9] ??ns disable mode 50 [9] ??ns input clock frequency v dd ? 4.75 v ? ? 49.2 mhz crcprs (prs mode) input clock frequency v dd ? 4.75 v ? ? 49.2 mhz crcprs (crc mode) input clock frequency ? ? 24.6 mhz spim input clock frequency ? ? 8.2 mhz the spi serial clock (sclk) frequency is equal to the input clock frequency divided by 2 spis input clock (sclk) frequency ? ? 4.1 mhz the input clock is the spi sclk in spis mode width of ss_negated between transmissions 50 [9] ??ns transmitter input clock frequency the baud rate is equal to the input clock frequency divided by 8 v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz receiver input clock frequency the baud rate is equal to the input clock frequency divided by 8 v dd ? 4.75 v, 2 stop bits ? ? 49.2 mhz v dd ? 4.75 v, 1 stop bit ? ? 24.6 mhz note 9. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period).
CY8CPLC20 document number: 001-48325 rev. *j page 38 of 56 9.4.5 ac analog output buffer specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. 9.4.6 ac external clock specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. table 9-3. 5v ac analog output buffer specifications symbol description min typ max units notes t rob rising settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 4 4 ? s ? s t sob falling settling time to 0.1%, 1 v step, 100 pf load power = low power = high ? ? ? ? 3.4 3.4 ? s ? s sr rob rising slew rate (20% to 80%), 1 v step, 100pf load power = low power = high 0.5 0.5 ? ? ? ? v/ ? s v/ ? s sr fob falling slew rate (80% to 20%), 1 v step, 100 pf load power = low power = high 0.55 0.55 ? ? ? ? v/ ? s v/ ? s bw ob small signal bandwidth, 20mv pp , 3db bw, 100 pf load power = low power = high 0.8 0.8 ? ? ? ? mhz mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100 pf load power = low power = high 300 300 ? ? ? ? khz khz note 10. 50 ns minimum input pulse width is based on the input syn chronizers running at 24 mhz (42 ns nominal period ) table 9-4. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.093 ? 24.6 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ?s
CY8CPLC20 document number: 001-48325 rev. *j page 39 of 56 9.4.7 ac programming specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ?? c ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. table 9-5. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 10 ? ms t write flash block write time ? 40 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns t eraseall flash erase time (bulk) ? 80 ? ms erase all blocks and protection fields at once t program_hot flash block erase + flash block write time ? ? 100 [11] ms 0 ? c <= tj <= 100 ? c t program_cold flash block erase + flash block write time ? ? 200 [11] ms ?40 ? c <= tj <= 0 ? c
CY8CPLC20 document number: 001-48325 rev. *j page 40 of 56 9.4.8 ac i 2 c specifications the following table lists guaranteed maximum and minimum specificat ions for the voltage and temperature ranges: 4.75 v to 5.25 v and ?40 ? cc ? t a ? 85 ? c. typical parameters are measured at 5 v at 25 ? c and are for design guidance only. figure 9-7. definition for timing for fast - /standard - mode on the i 2 c bus packaging dimensions table 9-6. ac characteristics of the i 2 c sda and scl pins symbol description standard-mode fast-mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? ? s t highi2c high period of the scl clock 4.0 ?0.6 ? ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? ? s t hddati2c data hold time 0 ?0 ? ? s t sudati2c data set-up time 250 ?100 [12] ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? ? s t spi2c pulse width of spikes suppressed by the input filter. ? ?050ns notes 11. for the full industrial range, the user must employ a temperat ure sensor user module (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 . 12. a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat ? 250 ns. this will automatically be the case if the device does not stretch the low period of the scl signal. if the device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i 2 c-bus specification) before the scl line is relea sed. i2c_sda i2c_scl s sr s p t bufi2c t spi2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c start condition repeated start condition stop condition
CY8CPLC20 document number: 001-48325 rev. *j page 41 of 56 10. packaging information this chapter illustrates the packaging specifications for the CY8CPLC20 plc device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the emulator pod dimension drawings at http://www.cypress.com . 10.1 packaging dimensions figure 10-1. 28-p in (210-mil) ssop 51-85079 *e
CY8CPLC20 document number: 001-48325 rev. *j page 42 of 56 figure 10-2. 48-pin (7 7 mm) qfn important notes for information on the preferred dimensions for mounting qfn packages, refer to application note, ?application notes for surfac e mount assembly of amkor's microleadframe (mlf) packages? available at http://www.amkor.com . pinned vias for thermal conduction are not required for the low-power psoc devices. pad exposed solderable 001-12919 *c
CY8CPLC20 document number: 001-48325 rev. *j page 43 of 56 figure 10-3. 48-pin qfn 7 7 0.90 mm (sawn type) 001-13191 *e
CY8CPLC20 document number: 001-48325 rev. *j page 44 of 56 figure 10-4. 100-pin tqfp 10.1 thermal impedances 51-85048 *e table 10-1. thermal impedances per package package typical ? ja [13] typical ? jc 28 ssop 59 ? c/w 23 ? c/w 48 qfn [14] 15 ? c/w 18 ? c/w 100 tqfp 42 ? c/w 15 ? c/w
CY8CPLC20 document number: 001-48325 rev. *j page 45 of 56 10.2 capacitance on crystal pins 10.3 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 10-2. typical package capacitance on crystal pins package package capacitance 28 ssop 2.8 pf 48 qfn 1.8 pf 100 tqfp 3.1 pf notes 13. t j = t a + power x ? ja 14. to achieve the thermal impedance specified for the qfn package, refer to "application notes for surface mount assembly of am kor's microleadframe (mlf) packages" available at http://www.amkor.com . table 10-3. solder reflow peak temperature package maximum peak temperature time at maximum peak temperature 28 ssop 260 ? c 30 s 48 qfn 260 ? c 30 s 100 tqfp 260 ? c 30 s
CY8CPLC20 document number: 001-48325 rev. *j page 46 of 56 11. development tool selection 11.1 software 11.1.1 psoc designer? at the core of the psoc development software suite is psoc designer, used to generate psoc firmware applications. psoc designer is available free of charge at http://www.cyp ress.com. psoc designer comes with a free c compiler. 11.1.2 psoc programmer psoc programmer is a very flexible programming application. it is used on the bench in development and is also suitable for factory programming. psoc programmer works either in a standalone configuration or operates directly from psoc designer or psoc express. psoc programmer software is compatible with both psoc ice cube in-circuit emulator and psoc miniprog. psoc programmer is available free of charge at http://www.cypress.com. 11.2 development kits all development kits are sold at the cypress online store . 11.2.1 cy3274 hv development kit the cy3274 is for prototyping and development on the CY8CPLC20 with psoc designer. this kit supports in-circuit emulation. the software interface enables users to run, halt, and single-step the processor and view the content of specific memory locations. psoc designer also supports the advanced emulation features. the hardware comprises of the high voltage coupling circuit for 110vac-240vac powerline, which is compliant with the cenelec/fcc standards. this board also has an onboard switch mode power supply. the kit comprises: one high voltage (110-230vac) plc board. cypress recom- mends that a user purchases two cy3274 kits to setup a two-node plc subsystem for evaluation and development. CY8CPLC20-ocd (100 tqfp) software cd supporting literature miniprog1 11.2.2 cy3275 lv development kit the cy3275-plc is for prototyping and development on the CY8CPLC20 with psoc designer. this kit supports in-circuit emulation. the software interface enables users to run, halt, and single-step the processor and view the content of specific memory locations. psoc designer also supports advanced emulation features. the hardware comprises of the low voltage coupling circuit for 12-24v ac/dc powerline. this board also has an onboard switch mode power supply. the kit comprises: one low voltage (12-24v ac/dc) plc board. cypress recom- mends that a user purchases two cy3275 kits to setup a two-node plc subsystem for evaluation and development. CY8CPLC20-ocd (100tqfp) software cd supporting literature miniprog1 11.2.3 cy3250-plc pod kits the cy3250-plc pod kits are essential for development purposes as they provide the users a medium to emulate and debug their designs. the pod kits are available for all the available footprints. the details are: cy3250-plc20nq ? one ssop pod (CY8CPLC20-ocd), two 28-ssop feet, one 3250-flex cable, one 28-ssop foot mask cy3250-plc20qfn ? one qfn pod (CY8CPLC20-ocd), two 48-qfn feet, one 3250-flex cable cy3250-plc20nq-pod ? two ssop pods (CY8CPLC20-ocd) cy3250-plc20qfn-pod ? two qfn pods (CY8CPLC20-ocd) 11.2.4 cy3215-dk basic development kit the cy3215-dk is for prototyping and development with psoc designer. this kit can be used in conjunction with the plc kits to support in-circuit emulation. the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. psoc designer also supports the advanced emulation features. the kit includes: psoc designer software cd ice-cube in-circuit emulator ice flex-pod for cy8c29x66 family cat-5 adapter mini-eval programming board 110 ~ 240v power supply, euro-plug adapter imagecraft c compiler issp cable usb 2.0 cable and blue cat-5 cable 2 cy8c29466-24pxi 28-pdip chip samples
CY8CPLC20 document number: 001-48325 rev. *j page 47 of 56 11.3 evaluation kits the evaluation kits do not have onboard powerline capability, but can be used with a plc kit for evaluation purposes. all evalu- ation tools are sold at the cypress online store. 11.3.1 cy3210-miniprog1 the cy3210-miniprog1 kit enables the user to program psoc devices via the miniprog1 programming unit. the miniprog is a small, compact prototyping programmer that connects to the pc via a provided usb 2.0 cable. the kit includes: miniprog programming unit minieval socket programming and evaluation board 28-pin cy8c29466-24pxi pdip psoc device sample 28-pin cy8c27443-24pxi pdip psoc device sample psoc designer software cd getting started guide usb 2.0 cable 11.3.2 cy3210-psoceval1 the cy3210-psoceval1 kit features an evaluation board and the miniprog1 programming unit. the evaluation board includes an lcd module, potentiometer, leds, and plenty of bread boarding space to meet all of your evaluation needs. the kit includes: evaluation board with lcd module miniprog programming unit 28-pin cy8c29466-24pxi pdip psoc device sample (2) psoc designer software cd getting started guide usb 2.0 cable 11.3.3 cy3214-psocevalusb the cy3214-psocevalusb evaluation kit features a devel- opment board for the cy8c24794-24lfxi psoc device. special features of the board include both usb and capacitive sensing development and debugging support. this evaluation board also includes an lcd module, potentiometer, leds, an enunciator, and plenty of bread boarding space to meet all of your evaluation needs. the kit includes: psocevalusb board lcd module miniprog programming unit mini usb cable psoc designer and example projects cd getting started guide wire pack 11.4 device programmers all device programmers are sold at the cypress online store. 11.4.1 cy3216 modular programmer the cy3216 modular programmer kit features a modular programmer and the miniprog1 programming unit. the modular programmer includes three programming module cards and supports multiple cypress products. the kit includes: modular programmer base 3 programming module cards miniprog programming unit psoc designer software cd getting started guide usb 2.0 cable 11.4.2 cy3207 issp in-system serial programmer (issp) the cy3207issp is a production programmer. it includes protection circuitry and an industrial case that is more robust than the miniprog in a production programming environment. note that cy3207issp needs special software and is not compatible with psoc programmer. the kit includes: cy3207 programmer unit psoc issp software cd 110 ~ 240v power supply, euro-plug adapter usb 2.0 cable
CY8CPLC20 document number: 001-48325 rev. *j page 48 of 56 12. ordering information the following table lists the CY8CPLC20 plc device s? key package features and ordering codes. 12.1 ordering code definitions table 12-1. CY8CPLC20 plc device key features and ordering information package ordering code flash (bytes) ram (bytes) temperature range digital psoc blocks analog psoc blocks digital i/o pins analog inputs analog outputs xres pin 28-pin (210 mil) ssop CY8CPLC20-28pvxi 32 k 2 k ?40 c to +85 c 16 12 24 12 4 yes 28-pin (210 mil) ssop (tape and reel) CY8CPLC20-28pvxit 32 k 2 k ?40 c to +85 c 16 12 24 12 4 yes 48-pin qfn [15] CY8CPLC20-48lfxi 32 k 2 k ?40 c to +85 c 16 12 44 12 4 yes 48-pin qfn (sawn) CY8CPLC20-48ltxi 32 k 2 k ?40 c to +85 c 16 12 44 12 4 yes 48-pin qfn (sawn) (tape and reel) CY8CPLC20-48ltxit 32 k 2 k ?40 c to +85 c 16 12 44 12 4 yes 100-pin ocd tqfp [16] CY8CPLC20-ocd 32 k 2 k ?40 c to +85 c 16 12 64 12 4 yes cy 8 c plc 20 - pc xxx package type: pvx = ssop pb.-free lfx/lkx/ltx/lqx/lcx = qfn pb-free pin count: 28/48 programmability: psoc core family code: powerline communication solution technology code: c = cmos marketing code: 8 = cypress psoc company id: cy = cypress notes 15. not recommended for new designs. 16. this part may be used for in-circuit debuggi ng. it is not available for production.
CY8CPLC20 document number: 001-48325 rev. *j page 49 of 56 13. acronyms 13.1 acronyms used table 13-1 lists the acronyms that are used in this document. table 13-1. acronyms used in this datasheet acronym description acronym description ac alternating current mcu microcontroller unit adc analog-to-digital converter mips million instructions per second api application programming interface ocd on-chip debug biu band-in-use pcb printed circuit board cmos complementary metal oxide semiconductor pdip plastic dual-in-line package cpu central processing unit pga programmable gain amplifier crc cyclic redundancy check plc powerline communication csma carrier sense multiple access pll phase-locked loop ct continuous time plt powerline transceiver dac digital-to-analog converter por power on reset dc direct current ppor precision power on reset dtmf dual-tone multi-frequency prs pseudo-random sequence eco external crystal oscillator psoc? programmable system-on-chip eeprom electrically erasable programmable read-only memory pwm pulse width modulator fsk frequency-shift keying qfn quad flat no leads gpio general-purpose i/o rtc real time clock i/o input/output sar successive approximation ice in-circuit emulator sc switched capacitor ide integrated development environment slimo slow imo ilo internal low speed oscillator spitm serial peripheral interface imo internal main oscillator sram static random access memory irda infrared data association srom supervisory read only memory issp in-system serial programmi ng ssop shrink smal l-outline package lcd liquid crystal display tqfp thin quad flat pack led light-emitting diode uart universal asynchronous reciever / trans- mitter lpc low power comparator usb universal serial bus lpf low pass filter wdt watchdog timer lvd low-voltage detect xres external reset mac multiply-accumulate
CY8CPLC20 document number: 001-48325 rev. *j page 50 of 56 14. reference documents CY8CPLC20, cy8cled16p01, cy8c29x66, cy8c27x43, cy8c24 x94, cy8c24x23, cy8c24x23a, cy8c22x13, cy8c21x34, cy8c21x23, cy7c64215, cy7c603xx, cy8cnp1xx, and cywu sb6953 psoc? programmable system-on-chip technical reference manual (trm) (001-14463) design aids ? reading and writing psoc ? flash ? an2015 (001-40459) understanding datasheet jitter specifications for cypress timing products ? an5054 (001-14503) estimating CY8CPLC20/cy8cled16p01 power consumption ? an55403 (001-55403) application notes for surface mount assembly of amkor's microleadframe (mlf) packages ? available at http://www.amkor.com . 15. document conventions 15.1 units of measure table 15-1 lists the unit sof measures. 15.2 numeric conventions hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexadecimal numbers may also be represented by a ?0x? pref ix, the c coding convention. binary numbers have an appended lowercase ?b? (for example, 01010100b? or ?01000011b?). nu mbers not indicated by an ?h?, ?b?, or 0x are decimals. table 15-1. units of measure symbol unit of measure symbol unit of measure kb 1024 bytes ms millisecond db decibels mv millivolts ? c degree celsius na nanoampere ff femto farad ns nanosecond khz kilohertz nv nanovolts k ? kilohm ppm parts per million mhz megahertz % percent a microampere pf picofarad f microfarad ps picosecond s microsecond pa pikoampere v microvolts rt-hz root hertz w microwatts v volts ma milliampere w watt mm millimeter active high 1. a logic signal having its asserted state as the logic 1 state. 2. a logic signal having the logic 1 state as the higher voltage of the two states. analog blocks the basic programmable opamp circuits. these are switched capacitor (sc) and continuous time (ct) blocks. these blocks c an be interconnected to provide adcs, dacs, multi-pole filters, gain stages, and much more. analog-to-digital (adc) a device that changes an analog signal to a digital signal of corresponding magnitude. typically, an adc converts a voltage to a digital number. the digital-to-analog (dac) converter performs the reverse operation. application programming interface (api) a series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). apis serve as building blocks for progr ammers that create software applications. asynchronous a signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
CY8CPLC20 document number: 001-48325 rev. *j page 51 of 56 bandgap reference a stable voltage reference design that matches the positive temperature coefficient of vt with the negative temperat ure coefficient of vbe, to produce a ze ro temperature coefficient (ideally) reference. bandwidth 1. the frequency range of a message or information processing system measured in hertz. 2. the width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. bias 1. a systematic deviation of a value from a reference value. 2. the amount by which the average of a set of values departs from a reference value. 3. the electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. block 1. a functional unit that performs a single function, such as an oscillator. 2. a functional unit that may be configured to perform one of several functions, such as a digital psoc block or an analog psoc block. buffer 1. a storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. usually refers to an area reserved for io operations, into which data is read, or from which data is written. 2. a portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. an amplifier used to lower the output impedance of a system. bus 1. a named connection of nets. bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. a set of signals performing a common function and carrying similar data. typically represented using vector notation; for example, address[7:0]. 3. one or more conductors that serve as a common connection for a group of related devices. clock the device that generates a periodic signal with a fixed fr equency and duty cycle. a clock is sometimes used to synchroni ze different logic blocks. comparator an electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. compiler a program that translates a high level language, such as c, into machine language. configuration space in psoc devices, the register space accessed when the xio bit, in the cpu_f register, is set to ?1?. crystal oscillator an oscillator in which the frequency is controlled by a piezoelectric crystal. typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy check (crc) a calculation used to detect errors in data communications, typically performed using a linear feedback shift register. similar calculations may be used for a variety of other purposes such as data compression. data bus a bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. more generally, a set of signals used to convey data between digital functions. debugger a hardware and software system that allo ws you to analyze the operation of the system under development. a debugger usually allows th e developer to step through the firmware one step at a time, set break points, and analyze memory.
CY8CPLC20 document number: 001-48325 rev. *j page 52 of 56 dead band a period of time when neither of two or more signals are in their active state or in transition. digital blocks the 8-bit logic blocks that can act as a counter, timer, se rial receiver, serial transmitter, crc generator, pseudo-random number generator, or spi. digital-to-analog (dac) a device that changes a digital signal to an analog signal of corresponding magnitude. the analog- to-digital (adc) converter performs the reverse operation. duty cycle the relations hip of a clock period high time to its low time, expressed as a percent. emulator duplicates (provides an emul ation of) the functions of one system with a different system, so that the second system appears to behave like the first system. external reset (xres) an active high signal that is driven into the psoc device. it causes all operation of the cpu and blocks to stop and return to a pre-defined state. flash an electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of eproms, pl us in-system erasability. non-volatile means that the data is retained when power is off. flash block the smallest amount of flash rom space that may be programmed at one time and the smallest amount of flash space that may be protected. a flash block holds 64 bytes. frequency the number of cycles or events pe r unit of time, for a periodic function. gain the ratio of output current, voltage, or power to input current, voltage, or power, respectively. gain is usually expressed in db. i 2 c a two-wire serial computer bus by philips semiconductors (now nxp semiconductors). i 2 c is an inter-integrated circuit. it is used to connec t low-speed peripherals in an embedded system. the original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system fo r building control electronics. i 2 c uses only two bi-directional pins, clock and data, both running at +5v and pulled high with resistors. the bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. ice the in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (psoc designer). input/output (i/o) a device that introduces data into or extracts data from a system. interrupt a suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. interrupt service routine (isr) a block of code that normal code execution is diverted to when the m8c receives a hardware interrupt. many interrupt sources may each exist with its own priority and individual isr code block. each isr code block ends with the reti instruction, returning the device to the point in the program where it left normal program execution. jitter 1. a misplacement of the timing of a transition from its ideal position. a typical form of corruption that occurs on serial data streams. 2. the abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequen cy or phase of successive cycles. low-voltage detect (lvd) a circuit that senses v dd and provides an interrupt to the system when v dd falls lower than a selected threshold.
CY8CPLC20 document number: 001-48325 rev. *j page 53 of 56 m8c an 8-bit harvard-architecture microprocessor. the microprocessor coordinates all activity inside a psoc by interfacing to the flash, sram, and register space. master device a device that controls the timing for data exchanges between two devices. or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. the controlled device is called the slave device . microcontroller an integrated circuit chip that is desi gned primarily for control systems and products. in addition to a cpu, a microcontroller typically includes memory, timing circuits, and io circuitry. the reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. this in turn, reduces the volume and the cost of the controller. the microcontroller is normally not used for general-purpose computation as is a microprocessor. mixed-signal the reference to a circuit containing both analog and digital techniques and components. modulator a device that imposes a signal on a carrier. noise 1. a disturbance that affects a signal and that may distort the information carried by the signal. 2. the random variations of one or more characteristi cs of any entity such as voltage, current, or data. oscillator a circuit that may be crystal controlled and is used to generate a clock frequency. parity a technique for testing transmitting data. typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). phase-locked loop (pll) an electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. pinouts the pin number assignment: the relation between the logical inputs and outputs of the psoc device and their physical counterparts in the printed circuit board (pcb) package. pinouts involve pin numbers as a link between schematic and pcb design (both being computer generated files) and may also involve pin names. port a group of pins, usually eight. power on reset (por) a circuit that forces the psoc device to reset when the voltage is lower than a pre-set level. this is a type of hardware reset. psoc ? cypress semiconductor?s psoc ? is a registered trademark and programmable system-on- chip? is a trademark of cypress. psoc designer? the software for cypress? programmable system-on-chip technology. pulse width modulator (pwm) an output in the form of duty cycle which varies as a function of the applied measurand ram an acronym for random access memory. a data-storage device from which data can be read out and new data can be written in. register a storage device with a specific capacity, such as a bit or byte. reset a means of bringing a system back to a know state. see hardware reset and software reset.
CY8CPLC20 document number: 001-48325 rev. *j page 54 of 56 rom an acronym for read only memory. a data-storage device from which data can be read out, but new data cannot be written in. serial 1. pertaining to a process in which all events occur one after the other. 2. pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. settling time the time it takes for an output signal or value to stabilize after the input has changed from one value to another. shift register a memory storage device that sequentially shif ts a word either left or right to output a stream of serial data. slave device a device that allows another device to control the timing for data exchanges between two devices. or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. the controlling device is called the master device. sram an acronym for static random access memory. a memory device where you can store and retrieve data at a high rate of speed. the term static is used because, after a value is loaded into an sram cell, it remains unchanged until it is explicitly al tered or until power is removed from the device. srom an acronym for supervisory read only memory . the srom holds code that is used to boot the device, calibrate circuitry, and perform flash operations. the functions of the srom may be accessed in normal user code, operating from flash. stop bit a signal following a character or block that prepares the receiving device to receive the next character or block. synchronous 1. a signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. a system whose operation is synchronized by a clock signal. tri-state a function whose output can adopt three stat es: 0, 1, and z (high-impedance). the function does not drive any value in the z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. uart a uart or universal asynchronous receiver-tra nsmitter translates between parallel bits of data and serial bits. user modules pre-build, pre-tested hardw are/firmware peripheral functions that take care of managing and configuring the lower level analog and digital psoc blocks. user modules also provide high level api (application programming interface) for the peripheral function. user space the bank 0 space of the register map. the re gisters in this bank are more likely to be modified during normal program execution and not just durin g initialization. registers in bank 1 are most likely to be modified only during the initialization phase of the program. v dd a name for a power net meaning "voltage drain." the most positive power supply signal. usually 5 v or 3.3 v. v ss a name for a power net meaning "voltage source." the most negative power supply signal. watchdog timer a timer that must be serviced periodically. if it is not serviced, the cpu resets after a specified period of time.
CY8CPLC20 document number: 001-48325 rev. *j page 55 of 56 16. document history page document title: cy 8cplc20 powerline communication solution document numb er: 001-48325 revision ecn orig. of change submission date description of change ** 2571957 ghh/pyrs 09/24/08 new datasheet *a 2731927 ghh/hmt/ dsg 07/06/09 added - configurable baud rates and fsk frequencies - plc pod kits for development purposes modified - pin information for all packages *b 2748537 ghh see ecn added sections on ?getting started? and ?document conventions? modified the following electrical parameters - fimo6 min: changed from 5.75 mhz to 5.5 mhz - fimo6 max: changed from 6.35 mhz to 6.5 mhz - spis (maximum input clock frequency): changed from 4.1 ns to 4.1 mhz - twrite (flash block write time): changed from 40 ms to 10 ms *c 2752799 ghh 08/17/09 posting to external web. *d 2759000 ghh 09/02/2009 fixed typos in the data sheet *e 2778970 fre 10/05/2009 added a table for dc por and lvd specifications updated dc gpio, ac chip-level, and ac programming specifications as follows: - modified fimo6, twrite, and power up imo to switch specifications - added ioh, iol, dcilo, f32k _u, tpowerup, teraseall, and srpower_up specifications added 48-pin qfn (sawn) package diagram and CY8CPLC20-48ltxi and CY8CPLC20-48ltxit part details in the ordering information table updated section 4 and tables 9-1, 9-2, and 9-3 to state the requirement to use the external crystal for plc protocol timing table 9-1 and figure 9-1: changed pins 9 and 25 from nc to rsvd table 9-2 and figure 9-2: changed pins 7 and 39 from nc to rsvd table 9-3 and figure 9-3: changed pins 14 and 77 from nc to rsvd tables 9-1, 9-2, 9-3: added explanatio n to connect a 0.1 uf capacitor between xtal_stability and vss. fixed minor typos. *f 2846686 fre 01/12/2010 add table of contents. update copyright and sales urls. update 28-pin ssop, 48-pin qfn, 48-pin qfn (sawn type) package diagrams. add footnote in ordering information tabl e of CY8CPLC20-48lfxi stating, ?not recommended for new designs.? add capacitor description to agnd pin. *g 2903114 njf 04/01/2010 updated cypress website links added t baketemp and t baketime parameters updated package diagrams *h 2938300 cgx 05/27/10 minor ecn to post to external website *i 3114960 njf 12/17/10 added dc i 2 c specifications table. added f 32k_u max limit. added tjit_imo specification, removed existing jitter specifications. updated dc analog reference tables and dc operational amplifier tables. updated units of measure, acronyms, glossary, and references sections. updated solder reflow specifications. no specific changes were made to ac digital block specifications table and i 2 c timing diagram. they were updated for clearer understanding. updated figure 9-5 since the labelling for y-axis was incorrect. removed footnote reference for ?solder reflow peak temperature? table. added the typical ? jc parameter to the thermal impedances table. table 7-1 and figure 7-1: changed pin 25 from rsvd to p0[2]. table 7-2 and figure 7-2: changed pin 39 from rsvd to p0[2]. table 7-3 and figure 7-3: changed pin 77 from rsvd to p0[2]. *j 3284994 shob 06/29/11 updated getting started , development tools , and designing with psoc designer .
document number: 001-48325 rev. *j revised june 29, 2011 page 56 of 56 CY8CPLC20 ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. 17. sales, solutions , and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . 17.1 products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless 17.2 psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5

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